04185fc67c
On the mv78xx0 development board, eth2 and eth3 do not have corresponding PHYs, but are internally connected, as a way of facilitating communication between the two CPU cores. Since there are no PHYs, we need to tell the network driver explicitly to force the link on eth2 and eth3 up, to 1000 Mb/s full duplex. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
/*
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* arch/arm/mach-mv78xx0/db78x00-bp-setup.c
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*
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* Marvell DB-78x00-BP Development Board Setup
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/ata_platform.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ethtool.h>
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#include <mach/mv78xx0.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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static struct mv643xx_eth_platform_data db78x00_ge00_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(8),
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};
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static struct mv643xx_eth_platform_data db78x00_ge01_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(9),
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};
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static struct mv643xx_eth_platform_data db78x00_ge10_data = {
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.phy_addr = MV643XX_ETH_PHY_NONE,
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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};
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static struct mv643xx_eth_platform_data db78x00_ge11_data = {
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.phy_addr = MV643XX_ETH_PHY_NONE,
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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};
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static struct mv_sata_platform_data db78x00_sata_data = {
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.n_ports = 2,
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};
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static void __init db78x00_init(void)
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{
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/*
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* Basic MV78xx0 setup. Needs to be called early.
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*/
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mv78xx0_init();
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/*
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* Partition on-chip peripherals between the two CPU cores.
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*/
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if (mv78xx0_core_index() == 0) {
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mv78xx0_ehci0_init();
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mv78xx0_ehci1_init();
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mv78xx0_ehci2_init();
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mv78xx0_ge00_init(&db78x00_ge00_data);
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mv78xx0_ge01_init(&db78x00_ge01_data);
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mv78xx0_ge10_init(&db78x00_ge10_data);
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mv78xx0_ge11_init(&db78x00_ge11_data);
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mv78xx0_sata_init(&db78x00_sata_data);
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mv78xx0_uart0_init();
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mv78xx0_uart2_init();
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} else {
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mv78xx0_uart1_init();
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mv78xx0_uart3_init();
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}
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}
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static int __init db78x00_pci_init(void)
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{
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if (machine_is_db78x00_bp()) {
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/*
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* Assign the x16 PCIe slot on the board to CPU core
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* #0, and let CPU core #1 have the four x1 slots.
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*/
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if (mv78xx0_core_index() == 0)
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mv78xx0_pcie_init(0, 1);
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else
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mv78xx0_pcie_init(1, 0);
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}
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return 0;
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}
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subsys_initcall(db78x00_pci_init);
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MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
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/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
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.phys_io = MV78XX0_REGS_PHYS_BASE,
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.io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.init_machine = db78x00_init,
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.map_io = mv78xx0_map_io,
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.init_irq = mv78xx0_init_irq,
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.timer = &mv78xx0_timer,
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MACHINE_END
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