0c3bd83b09
After the common MIPS CPU interrupt controller (for irq0-7) was introduced the Lasat boards didn't get their interrupts right, so nothing worked. The old routines need to be offset by the new 8 hardware interrupts common to all MIPS CPU's. Signed-off-by: Thomas Horsten <thomas@horsten.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
140 lines
3.5 KiB
C
140 lines
3.5 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Routines for generic manipulation of the interrupts found on the
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* Lasat boards.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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#include <asm/lasat/lasatint.h>
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#include <irq.h>
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static volatile int *lasat_int_status;
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static volatile int *lasat_int_mask;
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static volatile int lasat_int_mask_shift;
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void disable_lasat_irq(unsigned int irq_nr)
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{
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irq_nr -= LASAT_IRQ_BASE;
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*lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
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}
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void enable_lasat_irq(unsigned int irq_nr)
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{
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irq_nr -= LASAT_IRQ_BASE;
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*lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
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}
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static struct irq_chip lasat_irq_type = {
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.name = "Lasat",
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.ack = disable_lasat_irq,
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.mask = disable_lasat_irq,
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.mask_ack = disable_lasat_irq,
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.unmask = enable_lasat_irq,
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};
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static inline int ls1bit32(unsigned int x)
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{
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int b = 31, s;
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s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
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s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
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s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
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s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
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s = 1; if (x << 1 == 0) s = 0; b -= s;
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return b;
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}
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static unsigned long (*get_int_status)(void);
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static unsigned long get_int_status_100(void)
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{
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return *lasat_int_status & *lasat_int_mask;
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}
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static unsigned long get_int_status_200(void)
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{
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unsigned long int_status;
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int_status = *lasat_int_status;
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int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff;
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return int_status;
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long int_status;
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unsigned int cause = read_c0_cause();
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int irq;
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if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
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do_IRQ(7);
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return;
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}
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int_status = get_int_status();
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/* if int_status == 0, then the interrupt has already been cleared */
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if (int_status) {
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irq = LASAT_IRQ_BASE + ls1bit32(int_status);
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do_IRQ(irq);
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}
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}
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static struct irqaction cascade = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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void __init arch_init_irq(void)
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{
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int i;
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switch (mips_machtype) {
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case MACH_LASAT_100:
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lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
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lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
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lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
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get_int_status = get_int_status_100;
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*lasat_int_mask = 0;
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break;
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case MACH_LASAT_200:
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lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
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lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
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lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
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get_int_status = get_int_status_200;
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*lasat_int_mask &= 0xffff;
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break;
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default:
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panic("arch_init_irq: mips_machtype incorrect");
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}
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mips_cpu_irq_init();
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for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
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set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
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setup_irq(LASAT_CASCADE_IRQ, &cascade);
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}
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