64658743fd
Currently kernel images are limited to 8MB in size, and this causes problems especially when enabling features that take up a lot of kernel image space such as lockdep. The code now will align the kernel image size up to 4MB and map that many locked TLB entries. So, the only practical limitation is the number of available locked TLB entries which is 16 on Cheetah and 64 on pre-Cheetah sparc64 cpus. Niagara cpus don't actually have hw locked TLB entry support. Rather, the hypervisor transparently provides support for "locked" TLB entries since it runs with physical addressing and does the initial TLB miss processing. Fully utilizing this change requires some help from SILO, a patch for which will be submitted to the maintainer. Essentially, SILO will only currently map up to 8MB for the kernel image and that needs to be increased. Note that neither this patch nor the SILO bits will help with network booting. The openfirmware code will only map up to a certain amount of kernel image during a network boot and there isn't much we can to about that other than to implemented a layered network booting facility. Solaris has this, and calls it "wanboot" and we may implement something similar at some point. Signed-off-by: David S. Miller <davem@davemloft.net>
342 lines
9 KiB
C
342 lines
9 KiB
C
/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*/
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#ifndef _SPARC64_SPITFIRE_H
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#define _SPARC64_SPITFIRE_H
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#include <asm/asi.h>
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/* The following register addresses are accessible via ASI_DMMU
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* and ASI_IMMU, that is there is a distinct and unique copy of
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* each these registers for each TLB.
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*/
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#define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
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#define TLB_SFSR 0x0000000000000018 /* All chips */
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#define TSB_REG 0x0000000000000028 /* All chips */
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#define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
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#define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
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#define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
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#define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
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#define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
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#define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
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#define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
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/* These registers only exist as one entity, and are accessed
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* via ASI_DMMU only.
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*/
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#define PRIMARY_CONTEXT 0x0000000000000008
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#define SECONDARY_CONTEXT 0x0000000000000010
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#define DMMU_SFAR 0x0000000000000020
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#define VIRT_WATCHPOINT 0x0000000000000038
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#define PHYS_WATCHPOINT 0x0000000000000040
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#define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
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#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
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#define L1DCACHE_SIZE 0x4000
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#define SUN4V_CHIP_INVALID 0x00
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#define SUN4V_CHIP_NIAGARA1 0x01
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#define SUN4V_CHIP_NIAGARA2 0x02
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#define SUN4V_CHIP_UNKNOWN 0xff
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#ifndef __ASSEMBLY__
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enum ultra_tlb_layout {
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spitfire = 0,
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cheetah = 1,
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cheetah_plus = 2,
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hypervisor = 3,
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};
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extern enum ultra_tlb_layout tlb_type;
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extern int sun4v_chip_type;
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extern int cheetah_pcache_forced_on;
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extern void cheetah_enable_pcache(void);
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#define sparc64_highest_locked_tlbent() \
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(tlb_type == spitfire ? \
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SPITFIRE_HIGHEST_LOCKED_TLBENT : \
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CHEETAH_HIGHEST_LOCKED_TLBENT)
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extern int num_kernel_image_mappings;
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/* The data cache is write through, so this just invalidates the
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* specified line.
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*/
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static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
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}
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/* The instruction cache lines are flushed with this, but note that
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* this does not flush the pipeline. It is possible for a line to
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* get flushed but stale instructions to still be in the pipeline,
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* a flush instruction (to any address) is sufficient to handle
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* this issue after the line is invalidated.
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*/
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static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
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}
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static inline unsigned long spitfire_get_dtlb_data(int entry)
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{
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unsigned long data;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (data)
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: "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
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/* Clear TTE diag bits. */
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data &= ~0x0003fe0000000000UL;
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return data;
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}
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static inline unsigned long spitfire_get_dtlb_tag(int entry)
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{
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unsigned long tag;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (tag)
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: "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
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return tag;
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}
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static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (data), "r" (entry << 3),
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"i" (ASI_DTLB_DATA_ACCESS));
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}
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static inline unsigned long spitfire_get_itlb_data(int entry)
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{
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unsigned long data;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (data)
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: "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
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/* Clear TTE diag bits. */
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data &= ~0x0003fe0000000000UL;
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return data;
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}
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static inline unsigned long spitfire_get_itlb_tag(int entry)
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{
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unsigned long tag;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (tag)
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: "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
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return tag;
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}
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static inline void spitfire_put_itlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (data), "r" (entry << 3),
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"i" (ASI_ITLB_DATA_ACCESS));
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}
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static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
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}
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static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
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}
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/* Cheetah has "all non-locked" tlb flushes. */
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static inline void cheetah_flush_dtlb_all(void)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (0x80), "i" (ASI_DMMU_DEMAP));
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}
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static inline void cheetah_flush_itlb_all(void)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (0x80), "i" (ASI_IMMU_DEMAP));
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}
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/* Cheetah has a 4-tlb layout so direct access is a bit different.
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* The first two TLBs are fully assosciative, hold 16 entries, and are
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* used only for locked and >8K sized translations. One exists for
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* data accesses and one for instruction accesses.
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*
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* The third TLB is for data accesses to 8K non-locked translations, is
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* 2 way assosciative, and holds 512 entries. The fourth TLB is for
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* instruction accesses to 8K non-locked translations, is 2 way
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* assosciative, and holds 128 entries.
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*
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* Cheetah has some bug where bogus data can be returned from
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* ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
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* the problem for me. -DaveM
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*/
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static inline unsigned long cheetah_get_ldtlb_data(int entry)
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{
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unsigned long data;
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__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
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"ldxa [%1] %2, %0"
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: "=r" (data)
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: "r" ((0 << 16) | (entry << 3)),
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"i" (ASI_DTLB_DATA_ACCESS));
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return data;
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}
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static inline unsigned long cheetah_get_litlb_data(int entry)
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{
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unsigned long data;
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__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
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"ldxa [%1] %2, %0"
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: "=r" (data)
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: "r" ((0 << 16) | (entry << 3)),
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"i" (ASI_ITLB_DATA_ACCESS));
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return data;
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}
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static inline unsigned long cheetah_get_ldtlb_tag(int entry)
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{
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unsigned long tag;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (tag)
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: "r" ((0 << 16) | (entry << 3)),
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"i" (ASI_DTLB_TAG_READ));
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return tag;
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}
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static inline unsigned long cheetah_get_litlb_tag(int entry)
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{
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unsigned long tag;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (tag)
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: "r" ((0 << 16) | (entry << 3)),
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"i" (ASI_ITLB_TAG_READ));
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return tag;
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}
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static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (data),
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"r" ((0 << 16) | (entry << 3)),
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"i" (ASI_DTLB_DATA_ACCESS));
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}
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static inline void cheetah_put_litlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (data),
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"r" ((0 << 16) | (entry << 3)),
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"i" (ASI_ITLB_DATA_ACCESS));
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}
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static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
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{
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unsigned long data;
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__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
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"ldxa [%1] %2, %0"
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: "=r" (data)
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: "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
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return data;
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}
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static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
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{
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unsigned long tag;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (tag)
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: "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
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return tag;
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}
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static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (data),
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"r" ((tlb << 16) | (entry << 3)),
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"i" (ASI_DTLB_DATA_ACCESS));
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}
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static inline unsigned long cheetah_get_itlb_data(int entry)
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{
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unsigned long data;
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__asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
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"ldxa [%1] %2, %0"
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: "=r" (data)
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: "r" ((2 << 16) | (entry << 3)),
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"i" (ASI_ITLB_DATA_ACCESS));
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return data;
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}
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static inline unsigned long cheetah_get_itlb_tag(int entry)
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{
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unsigned long tag;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (tag)
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: "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
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return tag;
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}
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static inline void cheetah_put_itlb_data(int entry, unsigned long data)
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{
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__asm__ __volatile__("stxa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* No outputs */
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: "r" (data), "r" ((2 << 16) | (entry << 3)),
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"i" (ASI_ITLB_DATA_ACCESS));
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(_SPARC64_SPITFIRE_H) */
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