1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
521 lines
13 KiB
C
521 lines
13 KiB
C
/*
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* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
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* IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/iommu.h>
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#include "pci.h"
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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static struct pci_controller *u3_agp, *u3_ht;
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static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
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{
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for (; node != 0;node = node->sibling) {
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int * bus_range;
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unsigned int *class_code;
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int len;
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/* For PCI<->PCI bridges or CardBus bridges, we go down */
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class_code = (unsigned int *) get_property(node, "class-code", NULL);
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if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
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(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
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continue;
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bus_range = (int *) get_property(node, "bus-range", &len);
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if (bus_range != NULL && len > 2 * sizeof(int)) {
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if (bus_range[1] > higher)
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higher = bus_range[1];
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}
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higher = fixup_one_level_bus_range(node->child, higher);
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}
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return higher;
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}
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/* This routine fixes the "bus-range" property of all bridges in the
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* system since they tend to have their "last" member wrong on macs
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*
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* Note that the bus numbers manipulated here are OF bus numbers, they
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* are not Linux bus numbers.
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*/
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static void __init fixup_bus_range(struct device_node *bridge)
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{
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int * bus_range;
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int len;
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/* Lookup the "bus-range" property for the hose */
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bus_range = (int *) get_property(bridge, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s\n",
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bridge->full_name);
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return;
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}
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bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
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}
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#define U3_AGP_CFA0(devfn, off) \
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((1 << (unsigned long)PCI_SLOT(dev_fn)) \
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| (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
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| (((unsigned long)(off)) & 0xFCUL))
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#define U3_AGP_CFA1(bus, devfn, off) \
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((((unsigned long)(bus)) << 16) \
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|(((unsigned long)(devfn)) << 8) \
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|(((unsigned long)(off)) & 0xFCUL) \
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|1UL)
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static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
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u8 bus, u8 dev_fn, u8 offset)
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{
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unsigned int caddr;
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if (bus == hose->first_busno) {
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if (dev_fn < (11 << 3))
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return 0;
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caddr = U3_AGP_CFA0(dev_fn, offset);
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} else
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caddr = U3_AGP_CFA1(bus, dev_fn, offset);
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/* Uninorth will return garbage if we don't read back the value ! */
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do {
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out_le32(hose->cfg_addr, caddr);
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} while (in_le32(hose->cfg_addr) != caddr);
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offset &= 0x07;
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return ((unsigned long)hose->cfg_data) + offset;
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}
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static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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*val = in_8((u8 *)addr);
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break;
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case 2:
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*val = in_le16((u16 *)addr);
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break;
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default:
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*val = in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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out_8((u8 *)addr, val);
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(void) in_8((u8 *)addr);
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break;
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case 2:
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out_le16((u16 *)addr, val);
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(void) in_le16((u16 *)addr);
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break;
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default:
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out_le32((u32 *)addr, val);
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(void) in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops u3_agp_pci_ops =
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{
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u3_agp_read_config,
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u3_agp_write_config
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};
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#define U3_HT_CFA0(devfn, off) \
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((((unsigned long)devfn) << 8) | offset)
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#define U3_HT_CFA1(bus, devfn, off) \
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(U3_HT_CFA0(devfn, off) \
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+ (((unsigned long)bus) << 16) \
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+ 0x01000000UL)
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static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
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u8 bus, u8 devfn, u8 offset)
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{
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if (bus == hose->first_busno) {
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if (PCI_SLOT(devfn) == 0)
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return 0;
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return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
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} else
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return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
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}
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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*val = in_8((u8 *)addr);
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break;
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case 2:
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*val = in_le16((u16 *)addr);
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break;
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default:
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*val = in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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out_8((u8 *)addr, val);
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(void) in_8((u8 *)addr);
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break;
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case 2:
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out_le16((u16 *)addr, val);
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(void) in_le16((u16 *)addr);
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break;
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default:
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out_le32((u32 *)addr, val);
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(void) in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops u3_ht_pci_ops =
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{
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u3_ht_read_config,
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u3_ht_write_config
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};
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static void __init setup_u3_agp(struct pci_controller* hose)
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{
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/* On G5, we move AGP up to high bus number so we don't need
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* to reassign bus numbers for HT. If we ever have P2P bridges
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* on AGP, we'll have to move pci_assign_all_busses to the
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* pci_controller structure so we enable it for AGP and not for
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* HT childs.
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* We hard code the address because of the different size of
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* the reg address cell, we shall fix that by killing struct
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* reg_property and using some accessor functions instead
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*/
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hose->first_busno = 0xf0;
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hose->last_busno = 0xff;
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hose->ops = &u3_agp_pci_ops;
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hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
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hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
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u3_agp = hose;
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}
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static void __init setup_u3_ht(struct pci_controller* hose)
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{
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hose->ops = &u3_ht_pci_ops;
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/* We hard code the address because of the different size of
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* the reg address cell, we shall fix that by killing struct
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* reg_property and using some accessor functions instead
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*/
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hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
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hose->first_busno = 0;
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hose->last_busno = 0xef;
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u3_ht = hose;
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}
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static int __init add_bridge(struct device_node *dev)
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{
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int len;
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struct pci_controller *hose;
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char* disp_name;
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int *bus_range;
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int primary = 1;
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struct property *of_prop;
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DBG("Adding PCI host bridge %s\n", dev->full_name);
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bus_range = (int *) get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
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dev->full_name);
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}
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hose = alloc_bootmem(sizeof(struct pci_controller));
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if (hose == NULL)
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return -ENOMEM;
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pci_setup_pci_controller(hose);
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hose->arch_data = dev;
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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of_prop = alloc_bootmem(sizeof(struct property) +
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sizeof(hose->global_number));
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if (of_prop) {
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memset(of_prop, 0, sizeof(struct property));
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of_prop->name = "linux,pci-domain";
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of_prop->length = sizeof(hose->global_number);
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of_prop->value = (unsigned char *)&of_prop[1];
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memcpy(of_prop->value, &hose->global_number, sizeof(hose->global_number));
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prom_add_property(dev, of_prop);
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}
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disp_name = NULL;
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if (device_is_compatible(dev, "u3-agp")) {
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setup_u3_agp(hose);
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disp_name = "U3-AGP";
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primary = 0;
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} else if (device_is_compatible(dev, "u3-ht")) {
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setup_u3_ht(hose);
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disp_name = "U3-HT";
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primary = 1;
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}
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printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
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disp_name, hose->first_busno, hose->last_busno);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev);
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pci_setup_phb_io(hose, primary);
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/* Fixup "bus-range" OF property */
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fixup_bus_range(dev);
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return 0;
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}
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void __init maple_pcibios_fixup(void)
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{
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struct pci_dev *dev = NULL;
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DBG(" -> maple_pcibios_fixup\n");
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for_each_pci_dev(dev)
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pci_read_irq_line(dev);
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/* Do the mapping of the IO space */
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phbs_remap_io();
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DBG(" <- maple_pcibios_fixup\n");
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}
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static void __init maple_fixup_phb_resources(void)
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{
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struct pci_controller *hose, *tmp;
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
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hose->io_resource.start += offset;
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hose->io_resource.end += offset;
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printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
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hose->global_number,
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hose->io_resource.start, hose->io_resource.end);
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}
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}
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void __init maple_pci_init(void)
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{
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struct device_node *np, *root;
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struct device_node *ht = NULL;
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/* Probe root PCI hosts, that is on U3 the AGP host and the
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* HyperTransport host. That one is actually "kept" around
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* and actually added last as it's resource management relies
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* on the AGP resources to have been setup first
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*/
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root = of_find_node_by_path("/");
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if (root == NULL) {
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printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
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return;
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}
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for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
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if (np->name == NULL)
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continue;
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if (strcmp(np->name, "pci") == 0) {
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if (add_bridge(np) == 0)
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of_node_get(np);
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}
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if (strcmp(np->name, "ht") == 0) {
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of_node_get(np);
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ht = np;
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}
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}
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of_node_put(root);
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/* Now setup the HyperTransport host if we found any
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*/
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if (ht && add_bridge(ht) != 0)
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of_node_put(ht);
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/* Fixup the IO resources on our host bridges as the common code
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* does it only for childs of the host bridges
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*/
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maple_fixup_phb_resources();
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/* Setup the linkage between OF nodes and PHBs */
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pci_devs_phb_init();
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/* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
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* assume there is no P2P bridge on the AGP bus, which should be a
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* safe assumptions hopefully.
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*/
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if (u3_agp) {
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struct device_node *np = u3_agp->arch_data;
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np->busno = 0xf0;
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for (np = np->child; np; np = np->sibling)
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np->busno = 0xf0;
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}
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/* Tell pci.c to use the common resource allocation mecanism */
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pci_probe_only = 0;
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/* Allow all IO */
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io_page_mask = -1;
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}
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int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
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{
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struct device_node *np;
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int irq = channel ? 15 : 14;
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if (pdev->vendor != PCI_VENDOR_ID_AMD ||
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pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
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return irq;
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np = pci_device_to_OF_node(pdev);
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if (np == NULL)
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return irq;
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if (np->n_intrs < 2)
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return irq;
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return np->intrs[channel & 0x1].line;
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}
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/* XXX: To remove once all firmwares are ok */
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static void fixup_maple_ide(struct pci_dev* dev)
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{
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#if 0 /* Enable this to enable IDE port 0 */
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{
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u8 v;
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pci_read_config_byte(dev, 0x40, &v);
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v |= 2;
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pci_write_config_byte(dev, 0x40, v);
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}
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#endif
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#if 0 /* fix bus master base */
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pci_write_config_dword(dev, 0x20, 0xcc01);
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printk("old ide resource: %lx -> %lx \n",
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dev->resource[4].start, dev->resource[4].end);
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dev->resource[4].start = 0xcc00;
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dev->resource[4].end = 0xcc10;
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#endif
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#if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
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{
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struct pci_dev *apicdev;
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u32 v;
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|
|
|
apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
|
|
if (apicdev == NULL)
|
|
printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
|
|
else {
|
|
pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
|
|
pci_read_config_dword(apicdev, 0xf4, &v);
|
|
v &= ~0x00000022;
|
|
pci_write_config_dword(apicdev, 0xf4, v);
|
|
pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
|
|
pci_read_config_dword(apicdev, 0xf4, &v);
|
|
v &= ~0x00000022;
|
|
pci_write_config_dword(apicdev, 0xf4, v);
|
|
pci_dev_put(apicdev);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,
|
|
fixup_maple_ide);
|