7412b10f79
Squeeze three instructions out of the iop32x irq demuxer, and nine out of the iop33x irq demuxer by using the hardware vector generator. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
136 lines
2.8 KiB
C
136 lines
2.8 KiB
C
/*
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* linux/arch/arm/mach-iop33x/irq.c
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*
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* Generic IOP331 IRQ handling functionality
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*
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* Author: Dave Jiang <dave.jiang@intel.com>
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* Copyright (C) 2003 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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static u32 iop331_mask0 = 0;
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static u32 iop331_mask1 = 0;
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static inline void intctl_write0(u32 val)
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{
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// INTCTL0
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intctl_write1(u32 val)
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{
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// INTCTL1
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr_write0(u32 val)
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{
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// INTSTR0
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr_write1(u32 val)
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{
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// INTSTR1
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iop3xx_cp6_enable();
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asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intbase_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intsize_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static void
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iop331_irq_mask1 (unsigned int irq)
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{
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iop331_mask0 &= ~(1 << irq);
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intctl_write0(iop331_mask0);
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}
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static void
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iop331_irq_mask2 (unsigned int irq)
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{
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iop331_mask1 &= ~(1 << (irq - 32));
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intctl_write1(iop331_mask1);
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}
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static void
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iop331_irq_unmask1(unsigned int irq)
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{
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iop331_mask0 |= (1 << irq);
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intctl_write0(iop331_mask0);
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}
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static void
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iop331_irq_unmask2(unsigned int irq)
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{
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iop331_mask1 |= (1 << (irq - 32));
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intctl_write1(iop331_mask1);
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}
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struct irq_chip iop331_irqchip1 = {
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.name = "IOP-1",
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.ack = iop331_irq_mask1,
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.mask = iop331_irq_mask1,
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.unmask = iop331_irq_unmask1,
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};
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struct irq_chip iop331_irqchip2 = {
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.name = "IOP-2",
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.ack = iop331_irq_mask2,
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.mask = iop331_irq_mask2,
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.unmask = iop331_irq_unmask2,
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};
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void __init iop331_init_irq(void)
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{
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unsigned int i;
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intctl_write0(0); // disable all interrupts
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intctl_write1(0);
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intstr_write0(0); // treat all as IRQ
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intstr_write1(0);
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intbase_write(0);
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intsize_write(1);
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if(machine_is_iq80331()) // all interrupts are inputs to chip
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*IOP3XX_PCIIRSR = 0x0f;
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for(i = 0; i < NR_IRQS; i++)
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{
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set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
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set_irq_handler(i, do_level_IRQ);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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