74b265d4e0
We need to add plat-s3c to the build to get the headers that will go in here once moved from include/asm-arm so we may as well put some useful common s3c code in here to stop the errors generated form having nothing built. The cpu setup is now passed the cpu idcode and the table of supported cpus to s3c_init_cpu() to abstract the cpu identification out of the initial io setup. As well as moving the cpu initialisation code, we move the map of the board specific items up to the calling code as none of the map_io() functions actually do anything other than pass this to iotable_init(). This patch does not rename any of the init functions that will be common to s3c24xx and any other s3c architectures as this can be done at a later date as it will touch all the board support files which use functions such as s3c24xx_init_clocks() and s3c24xx_init_uarts(). Note, the header arch/arm/plat-s3c24xx/include/plat/cpu.h still has functions that are used by both the cpu and board initialisation functions. This means that each board has definitions specific to the cpu support included and the vice-versa. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
220 lines
5.4 KiB
C
220 lines
5.4 KiB
C
/* linux/arch/arm/plat-s3c24xx/cpu.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* http://www.simtec.co.uk/products/SWLINUX/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX CPU Support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/cacheflush.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/system-reset.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/s3c2400.h>
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#include <plat/s3c2410.h>
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#include <plat/s3c2412.h>
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#include "s3c244x.h"
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#include <plat/s3c2440.h>
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#include <plat/s3c2442.h>
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#include <plat/s3c2443.h>
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/* table of supported CPUs */
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static const char name_s3c2400[] = "S3C2400";
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static const char name_s3c2410[] = "S3C2410";
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static const char name_s3c2412[] = "S3C2412";
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static const char name_s3c2440[] = "S3C2440";
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static const char name_s3c2442[] = "S3C2442";
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static const char name_s3c2443[] = "S3C2443";
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static const char name_s3c2410a[] = "S3C2410A";
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static const char name_s3c2440a[] = "S3C2440A";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = 0x32410000,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_clocks = s3c2410_init_clocks,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410_init,
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.name = name_s3c2410
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},
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{
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.idcode = 0x32410002,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_clocks = s3c2410_init_clocks,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410_init,
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.name = name_s3c2410a
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},
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{
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.idcode = 0x32440000,
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.idmask = 0xffffffff,
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.map_io = s3c244x_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440
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},
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{
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.idcode = 0x32440001,
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.idmask = 0xffffffff,
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.map_io = s3c244x_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440a
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},
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{
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.idcode = 0x32440aaa,
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.idmask = 0xffffffff,
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.map_io = s3c244x_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2442_init,
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.name = name_s3c2442
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},
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{
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.idcode = 0x32412001,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_clocks = s3c2412_init_clocks,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{ /* a newer version of the s3c2412 */
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.idcode = 0x32412003,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_clocks = s3c2412_init_clocks,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{
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.idcode = 0x32443001,
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.idmask = 0xffffffff,
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.map_io = s3c2443_map_io,
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.init_clocks = s3c2443_init_clocks,
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.init_uarts = s3c2443_init_uarts,
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.init = s3c2443_init,
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.name = name_s3c2443,
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},
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{
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.idcode = 0x0, /* S3C2400 doesn't have an idcode */
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.idmask = 0xffffffff,
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.map_io = s3c2400_map_io,
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.init_clocks = s3c2400_init_clocks,
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.init_uarts = s3c2400_init_uarts,
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.init = s3c2400_init,
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.name = name_s3c2400
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},
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};
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/* minimal IO mapping */
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static struct map_desc s3c_iodesc[] __initdata = {
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IODESC_ENT(GPIO),
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IODESC_ENT(IRQ),
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IODESC_ENT(MEMCTRL),
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IODESC_ENT(UART)
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};
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/* read cpu identificaiton code */
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static unsigned long s3c24xx_read_idcode_v5(void)
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{
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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return __raw_readl(S3C2412_GSTATUS1);
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#else
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return 1UL; /* don't look like an 2400 */
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#endif
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}
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static unsigned long s3c24xx_read_idcode_v4(void)
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{
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#ifndef CONFIG_CPU_S3C2400
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return __raw_readl(S3C2410_GSTATUS1);
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#else
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return 0UL;
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#endif
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}
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/* Hook for arm_pm_restart to ensure we execute the reset code
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* with the caches enabled. It seems at least the S3C2440 has a problem
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* resetting if there is bus activity interrupted by the reset.
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*/
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static void s3c24xx_pm_restart(char mode)
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{
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if (mode != 's') {
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unsigned long flags;
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local_irq_save(flags);
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__cpuc_flush_kern_all();
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__cpuc_flush_user_all();
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arch_reset(mode);
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local_irq_restore(flags);
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}
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/* fallback, or unhandled */
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arm_machine_restart(mode);
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}
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void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
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{
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unsigned long idcode = 0x0;
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/* initialise the io descriptors we need for initialisation */
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iotable_init(mach_desc, size);
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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if (cpu_architecture() >= CPU_ARCH_ARMv5) {
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idcode = s3c24xx_read_idcode_v5();
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} else {
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idcode = s3c24xx_read_idcode_v4();
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}
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arm_pm_restart = s3c24xx_pm_restart;
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s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
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}
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