5d2efba64b
The 10Gigabit ethernet device drivers appear to be able to chew up all 256MB of TCE mappings on pSeries systems, as evidenced by numerous error messages: iommu_alloc failed, tbl c0000000010d5c48 vaddr c0000000d875eff0 npages 1 Some experimentation indicates that this is essentially because one 1500 byte ethernet MTU gets mapped as a 64K DMA region when the large 64K pages are enabled. Thus, it doesn't take much to exhaust all of the available DMA mappings for a high-speed card. This patch changes the iommu allocator to work with its own unique, distinct page size. Although the patch is long, its actually quite simple: it just #defines a distinct IOMMU_PAGE_SIZE and then uses this in all the places that matter. As a side effect, it also dramatically improves network performance on platforms with H-calls on iommu translation inserts/removes (since we no longer call it 16 times for a 1500 bytes packet when the iommu HW is still 4k). In the future, we might want to make the IOMMU_PAGE_SIZE a variable in the iommu_table instance, thus allowing support for different HW page sizes in the iommu itself. Signed-off-by: Linas Vepstas <linas@austin.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/*
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _POWERPC_SYSDEV_DART_H
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#define _POWERPC_SYSDEV_DART_H
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/* Offset from base to control register */
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#define DART_CNTL 0
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/* Offset from base to exception register */
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#define DART_EXCP_U3 0x10
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/* Offset from base to TLB tag registers */
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#define DART_TAGS_U3 0x1000
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/* U4 registers */
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#define DART_BASE_U4 0x10
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#define DART_SIZE_U4 0x20
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#define DART_EXCP_U4 0x30
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#define DART_TAGS_U4 0x1000
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/* Control Register fields */
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/* U3 registers */
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#define DART_CNTL_U3_BASE_MASK 0xfffff
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#define DART_CNTL_U3_BASE_SHIFT 12
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#define DART_CNTL_U3_FLUSHTLB 0x400
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#define DART_CNTL_U3_ENABLE 0x200
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#define DART_CNTL_U3_SIZE_MASK 0x1ff
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#define DART_CNTL_U3_SIZE_SHIFT 0
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/* U4 registers */
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#define DART_BASE_U4_BASE_MASK 0xffffff
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#define DART_BASE_U4_BASE_SHIFT 0
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#define DART_CNTL_U4_ENABLE 0x80000000
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#define DART_CNTL_U4_IONE 0x40000000
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#define DART_CNTL_U4_FLUSHTLB 0x20000000
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#define DART_CNTL_U4_IDLE 0x10000000
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#define DART_CNTL_U4_PAR_EN 0x08000000
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#define DART_CNTL_U4_IONE_MASK 0x07ffffff
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#define DART_SIZE_U4_SIZE_MASK 0x1fff
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#define DART_SIZE_U4_SIZE_SHIFT 0
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#define DART_REG(r) (dart + ((r) >> 2))
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#define DART_IN(r) (in_be32(DART_REG(r)))
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#define DART_OUT(r,v) (out_be32(DART_REG(r), (v)))
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/* size of table in pages */
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/* DART table fields */
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#define DARTMAP_VALID 0x80000000
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#define DARTMAP_RPNMASK 0x00ffffff
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#define DART_PAGE_SHIFT 12
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#define DART_PAGE_SIZE (1 << DART_PAGE_SHIFT)
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#endif /* _POWERPC_SYSDEV_DART_H */
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