84db8d7cdb
Leaving include/asm/arch alone for now. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
349 lines
11 KiB
C
349 lines
11 KiB
C
#ifndef __ASM_AVR32_DMA_MAPPING_H
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#define __ASM_AVR32_DMA_MAPPING_H
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#include <linux/mm.h>
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#include <linux/device.h>
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#include <linux/scatterlist.h>
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#include <asm/processor.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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int direction);
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/*
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* Return whether the given device DMA address mask can be supported
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* properly. For example, if your device can only drive the low 24-bits
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* during bus mastering, then you would pass 0x00ffffff as the mask
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* to this function.
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*/
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static inline int dma_supported(struct device *dev, u64 mask)
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{
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/* Fix when needed. I really don't know of any limitations */
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return 1;
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}
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static inline int dma_set_mask(struct device *dev, u64 dma_mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, dma_mask))
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return -EIO;
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*dev->dma_mask = dma_mask;
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return 0;
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}
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/*
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* dma_map_single can't fail as it is implemented now.
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*/
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static inline int dma_mapping_error(struct device *dev, dma_addr_t addr)
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{
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return 0;
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}
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/**
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* dma_alloc_coherent - allocate consistent memory for DMA
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @size: required memory size
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* @handle: bus-specific DMA address
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*
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* Allocate some uncached, unbuffered memory for a device for
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* performing DMA. This function allocates pages, and will
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* return the CPU-viewed address, and sets @handle to be the
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* device-viewed address.
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*/
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extern void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *handle, gfp_t gfp);
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/**
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* dma_free_coherent - free memory allocated by dma_alloc_coherent
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @size: size of memory originally requested in dma_alloc_coherent
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* @cpu_addr: CPU-view address returned from dma_alloc_coherent
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* @handle: device-view address returned from dma_alloc_coherent
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*
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* Free (and unmap) a DMA buffer previously allocated by
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* dma_alloc_coherent().
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*
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* References to memory and mappings associated with cpu_addr/handle
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* during and after this call executing are illegal.
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*/
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extern void dma_free_coherent(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t handle);
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/**
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* dma_alloc_writecombine - allocate write-combining memory for DMA
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @size: required memory size
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* @handle: bus-specific DMA address
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*
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* Allocate some uncached, buffered memory for a device for
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* performing DMA. This function allocates pages, and will
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* return the CPU-viewed address, and sets @handle to be the
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* device-viewed address.
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*/
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extern void *dma_alloc_writecombine(struct device *dev, size_t size,
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dma_addr_t *handle, gfp_t gfp);
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/**
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* dma_free_coherent - free memory allocated by dma_alloc_writecombine
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @size: size of memory originally requested in dma_alloc_writecombine
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* @cpu_addr: CPU-view address returned from dma_alloc_writecombine
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* @handle: device-view address returned from dma_alloc_writecombine
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*
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* Free (and unmap) a DMA buffer previously allocated by
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* dma_alloc_writecombine().
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*
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* References to memory and mappings associated with cpu_addr/handle
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* during and after this call executing are illegal.
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*/
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extern void dma_free_writecombine(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t handle);
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/**
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* dma_map_single - map a single buffer for streaming DMA
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @cpu_addr: CPU direct mapped address of buffer
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* @size: size of buffer to map
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* @dir: DMA transfer direction
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*
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* Ensure that any data held in the cache is appropriately discarded
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* or written back.
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*
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* The device owns this memory once this call has completed. The CPU
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* can regain ownership by calling dma_unmap_single() or dma_sync_single().
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*/
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static inline dma_addr_t
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dma_map_single(struct device *dev, void *cpu_addr, size_t size,
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enum dma_data_direction direction)
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{
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dma_cache_sync(dev, cpu_addr, size, direction);
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return virt_to_bus(cpu_addr);
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}
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/**
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* dma_unmap_single - unmap a single buffer previously mapped
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @handle: DMA address of buffer
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* @size: size of buffer to map
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* @dir: DMA transfer direction
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*
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* Unmap a single streaming mode DMA translation. The handle and size
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* must match what was provided in the previous dma_map_single() call.
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* All other usages are undefined.
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*
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* After this call, reads by the CPU to the buffer are guaranteed to see
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* whatever the device wrote there.
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*/
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static inline void
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dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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}
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/**
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* dma_map_page - map a portion of a page for streaming DMA
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @page: page that buffer resides in
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* @offset: offset into page for start of buffer
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* @size: size of buffer to map
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* @dir: DMA transfer direction
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*
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* Ensure that any data held in the cache is appropriately discarded
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* or written back.
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*
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* The device owns this memory once this call has completed. The CPU
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* can regain ownership by calling dma_unmap_page() or dma_sync_single().
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*/
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static inline dma_addr_t
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dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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return dma_map_single(dev, page_address(page) + offset,
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size, direction);
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}
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/**
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* dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @handle: DMA address of buffer
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* @size: size of buffer to map
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* @dir: DMA transfer direction
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*
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* Unmap a single streaming mode DMA translation. The handle and size
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* must match what was provided in the previous dma_map_single() call.
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* All other usages are undefined.
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*
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* After this call, reads by the CPU to the buffer are guaranteed to see
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* whatever the device wrote there.
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*/
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static inline void
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dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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enum dma_data_direction direction)
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{
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dma_unmap_single(dev, dma_address, size, direction);
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}
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/**
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* dma_map_sg - map a set of SG buffers for streaming mode DMA
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @sg: list of buffers
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* @nents: number of buffers to map
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* @dir: DMA transfer direction
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*
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* Map a set of buffers described by scatterlist in streaming
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* mode for DMA. This is the scatter-gather version of the
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* above pci_map_single interface. Here the scatter gather list
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* elements are each tagged with the appropriate dma address
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* and length. They are obtained via sg_dma_{address,length}(SG).
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*
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* NOTE: An implementation may be able to use a smaller number of
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* DMA address/length pairs than there are SG table elements.
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* (for example via virtual mapping capabilities)
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* The routine returns the number of addr/length pairs actually
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* used, at most nents.
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*
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* Device ownership issues as mentioned above for pci_map_single are
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* the same here.
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*/
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static inline int
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dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction direction)
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{
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int i;
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for (i = 0; i < nents; i++) {
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char *virt;
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sg[i].dma_address = page_to_bus(sg_page(&sg[i])) + sg[i].offset;
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virt = sg_virt(&sg[i]);
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dma_cache_sync(dev, virt, sg[i].length, direction);
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}
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return nents;
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}
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/**
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* dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @sg: list of buffers
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* @nents: number of buffers to map
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* @dir: DMA transfer direction
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*
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* Unmap a set of streaming mode DMA translations.
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* Again, CPU read rules concerning calls here are the same as for
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* pci_unmap_single() above.
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*/
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static inline void
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dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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enum dma_data_direction direction)
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{
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}
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/**
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* dma_sync_single_for_cpu
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @handle: DMA address of buffer
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* @size: size of buffer to map
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* @dir: DMA transfer direction
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*
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* Make physical memory consistent for a single streaming mode DMA
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* translation after a transfer.
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*
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* If you perform a dma_map_single() but wish to interrogate the
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* buffer using the cpu, yet do not wish to teardown the DMA mapping,
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* you must call this function before doing so. At the next point you
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* give the DMA address back to the card, you must first perform a
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* dma_sync_single_for_device, and then the device again owns the
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* buffer.
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*/
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static inline void
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dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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/*
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* No need to do anything since the CPU isn't supposed to
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* touch this memory after we flushed it at mapping- or
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* sync-for-device time.
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*/
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}
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static inline void
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dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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dma_cache_sync(dev, bus_to_virt(dma_handle), size, direction);
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}
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static inline void
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dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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/* just sync everything, that's all the pci API can do */
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dma_sync_single_for_cpu(dev, dma_handle, offset+size, direction);
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}
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static inline void
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dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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/* just sync everything, that's all the pci API can do */
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dma_sync_single_for_device(dev, dma_handle, offset+size, direction);
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}
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/**
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* dma_sync_sg_for_cpu
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* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
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* @sg: list of buffers
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* @nents: number of buffers to map
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* @dir: DMA transfer direction
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*
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* Make physical memory consistent for a set of streaming
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* mode DMA translations after a transfer.
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*
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* The same as dma_sync_single_for_* but for a scatter-gather list,
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* same rules and usage.
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*/
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static inline void
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dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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/*
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* No need to do anything since the CPU isn't supposed to
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* touch this memory after we flushed it at mapping- or
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* sync-for-device time.
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*/
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}
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static inline void
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dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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int i;
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for (i = 0; i < nents; i++) {
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dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, direction);
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}
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}
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/* Now for the API extensions over the pci_ one */
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
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{
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return 1;
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}
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static inline int dma_get_cache_alignment(void)
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{
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return boot_cpu_data.dcache.linesz;
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}
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#endif /* __ASM_AVR32_DMA_MAPPING_H */
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