b915341b4b
In SGMII riser card different PHY chip are used with different external IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we should add another group of PHY nodes for SGMII mode. For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3. For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1. For P2020DS IRQ5 is used for PHY1~PHY2. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
428 lines
10 KiB
Text
428 lines
10 KiB
Text
/*
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* MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&board_lbc {
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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reg = <0x0 0x03000000>;
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label = "ramdisk-nor";
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};
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partition@3000000 {
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reg = <0x03000000 0x00e00000>;
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label = "diagnostic-nor";
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read-only;
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};
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partition@3e00000 {
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reg = <0x03e00000 0x00200000>;
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label = "dink-nor";
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read-only;
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};
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partition@4000000 {
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reg = <0x04000000 0x00400000>;
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label = "kernel-nor";
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};
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partition@4400000 {
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reg = <0x04400000 0x03b00000>;
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label = "fs-nor";
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};
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partition@7f00000 {
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reg = <0x07f00000 0x00060000>;
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label = "dtb-nor";
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};
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partition@7f60000 {
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reg = <0x07f60000 0x00020000>;
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label = "env-nor";
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read-only;
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};
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partition@7f80000 {
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reg = <0x07f80000 0x00080000>;
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label = "u-boot-nor";
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read-only;
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};
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x2 0x0 0x40000>;
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partition@0 {
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reg = <0x0 0x02000000>;
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label = "u-boot-nand";
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read-only;
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};
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partition@2000000 {
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reg = <0x02000000 0x10000000>;
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label = "fs-nand";
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};
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partition@12000000 {
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reg = <0x12000000 0x08000000>;
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label = "ramdisk-nand";
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};
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partition@1a000000 {
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reg = <0x1a000000 0x04000000>;
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label = "kernel-nand";
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};
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partition@1e000000 {
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reg = <0x1e000000 0x01000000>;
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label = "dtb-nand";
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};
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partition@1f000000 {
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reg = <0x1f000000 0x21000000>;
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label = "empty-nand";
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};
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};
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nand@4,0 {
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x4 0x0 0x40000>;
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};
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nand@5,0 {
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x5 0x0 0x40000>;
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};
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nand@6,0 {
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x6 0x0 0x40000>;
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};
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};
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&board_soc {
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupts = <10 1 0 0>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <10 1 0 0>;
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reg = <0x1>;
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};
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phy2: ethernet-phy@2 {
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interrupts = <10 1 0 0>;
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reg = <0x2>;
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};
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phy3: ethernet-phy@3 {
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interrupts = <10 1 0 0>;
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reg = <0x3>;
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};
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sgmii_phy0: sgmii-phy@0 {
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interrupts = <6 1 0 0>;
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reg = <0x1c>;
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};
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sgmii_phy1: sgmii-phy@1 {
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interrupts = <6 1 0 0>;
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reg = <0x1d>;
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};
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sgmii_phy2: sgmii-phy@2 {
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interrupts = <7 1 0 0>;
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reg = <0x1e>;
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};
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sgmii_phy3: sgmii-phy@3 {
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interrupts = <7 1 0 0>;
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reg = <0x1f>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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ptp_clock@24e00 {
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fsl,tclk-period = <5>;
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fsl,tmr-prsc = <200>;
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fsl,tmr-add = <0xAAAAAAAB>;
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fsl,tmr-fiper1 = <0x3B9AC9FB>;
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fsl,tmr-fiper2 = <0x3B9AC9FB>;
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fsl,max-adj = <499999999>;
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet2: ethernet@26000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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phy-connection-type = "rgmii-id";
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};
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mdio@26520 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet3: ethernet@27000 {
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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};
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mdio@27520 {
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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&board_pci0 {
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pcie@0 {
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interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 func 0 - PCI slot 1 */
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0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x11 func 1 - PCI slot 1 */
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0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x11 func 2 - PCI slot 1 */
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0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x11 func 3 - PCI slot 1 */
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0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x11 func 4 - PCI slot 1 */
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0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x11 func 5 - PCI slot 1 */
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0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x11 func 6 - PCI slot 1 */
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0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x11 func 7 - PCI slot 1 */
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0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x12 func 0 - PCI slot 2 */
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0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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/* IDSEL 0x12 func 1 - PCI slot 2 */
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0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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/* IDSEL 0x12 func 2 - PCI slot 2 */
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0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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/* IDSEL 0x12 func 3 - PCI slot 2 */
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0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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/* IDSEL 0x12 func 4 - PCI slot 2 */
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0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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/* IDSEL 0x12 func 5 - PCI slot 2 */
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0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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/* IDSEL 0x12 func 6 - PCI slot 2 */
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0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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/* IDSEL 0x12 func 7 - PCI slot 2 */
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0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
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// IDSEL 0x1c USB
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0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
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0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
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0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
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0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
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// IDSEL 0x1d Audio
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0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
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// IDSEL 0x1e Legacy
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0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
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0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
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// IDSEL 0x1f IDE/SATA
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0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
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0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
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>;
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uli1575@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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isa@1e {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <0xf000 0x0 0x0 0x0 0x0>;
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ranges = <0x1 0x0 0x1000000 0x0 0x0
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0x1000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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reg = <0x1 0x20 0x2
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0x1 0xa0 0x2
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0x1 0x4d0 0x2>;
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interrupt-controller;
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device_type = "interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <9 2 0 0>;
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interrupt-parent = <&mpic>;
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};
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i8042@60 {
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#size-cells = <0>;
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#address-cells = <1>;
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reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
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interrupts = <1 3 12 3>;
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interrupt-parent =
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<&i8259>;
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keyboard@0 {
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reg = <0x0>;
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compatible = "pnpPNP,303";
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};
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mouse@1 {
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reg = <0x1>;
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compatible = "pnpPNP,f03";
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};
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <0x1 0x70 0x2>;
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};
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gpio@400 {
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reg = <0x1 0x400 0x80>;
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};
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};
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};
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};
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};
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