d1cf1c7db3
Updates to u-boot allow this board to boot off of either the 8MB soldered on flash, or the 64MB SODIMM flash. This is achieved by changing JP12 and SW2.8 which in turn swaps which flash device appears on /CS0 and /CS6 respectively. Since the flash devices are not the same size, this also changes the MTD memory map layout on the local bus. Here we split the common chunks out into a pre and post include, so they can be reused by an upcoming "alternative boot" dts file; leaving only the local bus chunk behind. No content changes are made at this point - it is just purely the move to using include files. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
52 lines
1.1 KiB
Text
52 lines
1.1 KiB
Text
/*
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* SBC8548 Device Tree Source
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*
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* Copyright 2007 Wind River Systems Inc.
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*
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* Paul Gortmaker (see MAINTAINERS for contact information)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/{
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model = "SBC8548";
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compatible = "SBC8548";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8548@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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};
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