7c4dbbd87c
Update the ASoC documentation. Along with minor formatting and grammar cleanups it moves the ASoC overview into the present tense to reflect the fact that it has now been merged. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
51 lines
1.5 KiB
Text
51 lines
1.5 KiB
Text
Audio Clocking
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==============
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This text describes the audio clocking terms in ASoC and digital audio in
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general. Note: Audio clocking can be complex!
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Master Clock
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------------
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Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
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or SYSCLK). This audio master clock can be derived from a number of sources
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(e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
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audio playback and capture sample rates.
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Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
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their speed can be altered by software (depending on the system use and to save
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power). Other master clocks are fixed at a set frequency (i.e. crystals).
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DAI Clocks
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----------
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The Digital Audio Interface is usually driven by a Bit Clock (often referred to
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as BCLK). This clock is used to drive the digital audio data across the link
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between the codec and CPU.
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The DAI also has a frame clock to signal the start of each audio frame. This
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clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
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runs at exactly the sample rate (LRC = Rate).
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Bit Clock can be generated as follows:-
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BCLK = MCLK / x
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or
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BCLK = LRC * x
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or
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BCLK = LRC * Channels * Word Size
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This relationship depends on the codec or SoC CPU in particular. In general
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it is best to configure BCLK to the lowest possible speed (depending on your
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rate, number of channels and word size) to save on power.
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It is also desirable to use the codec (if possible) to drive (or master) the
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audio clocks as it usually gives more accurate sample rates than the CPU.
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