1b3c5cdab4
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
180 lines
3.9 KiB
Text
180 lines
3.9 KiB
Text
/*
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* MPC8349E-mITX-GP Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8349EMITXGP";
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compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8349@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>;
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i-cache-line-size = <20>;
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d-cache-size = <8000>;
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i-cache-size = <8000>;
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 10000000>;
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};
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soc8349@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00000200>;
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bus-frequency = <0>; // from bootloader
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <200 100>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <e 8>;
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interrupt-parent = < &ipic >;
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dfsrr;
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};
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i2c@3100 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3100 100>;
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interrupts = <f 8>;
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interrupt-parent = < &ipic >;
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dfsrr;
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};
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spi@7000 {
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device_type = "spi";
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compatible = "mpc83xx_spi";
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reg = <7000 1000>;
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interrupts = <10 8>;
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interrupt-parent = < &ipic >;
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mode = <0>;
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};
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usb@23000 {
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device_type = "usb";
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compatible = "fsl-usb2-dr";
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reg = <23000 1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = < &ipic >;
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interrupts = <26 8>;
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dr_mode = "otg";
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phy_type = "ulpi";
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};
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mdio@24520 {
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device_type = "mdio";
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compatible = "gianfar";
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reg = <24520 20>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Vitesse 8201 */
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phy1c: ethernet-phy@1c {
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interrupt-parent = < &ipic >;
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interrupts = <12 8>;
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reg = <1c>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <20 8 21 8 22 8>;
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interrupt-parent = < &ipic >;
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phy-handle = < &phy1c >;
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};
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>; // from bootloader
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interrupts = <9 8>;
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interrupt-parent = < &ipic >;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>; // from bootloader
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interrupts = <a 8>;
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interrupt-parent = < &ipic >;
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 10000>;
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interrupts = <b 8>;
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interrupt-parent = < &ipic >;
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num-channels = <4>;
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channel-fifo-len = <18>;
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exec-units-mask = <0000007e>;
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descriptor-types-mask = <01010ebf>;
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};
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ipic: pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <700 100>;
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device_type = "ipic";
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};
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};
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pci@e0008600 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0F - PCI Slot */
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7800 0 0 1 &ipic 14 8 /* PCI_INTA */
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7800 0 0 2 &ipic 15 8 /* PCI_INTB */
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>;
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interrupt-parent = < &ipic >;
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interrupts = <43 8>;
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bus-range = <1 1>;
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ranges = <42000000 0 a0000000 a0000000 0 10000000
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02000000 0 b0000000 b0000000 0 10000000
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01000000 0 00000000 e3000000 0 01000000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008600 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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