36f31a7084
This patch removes lcdcon1 register field from the s3c2410fb_display as all bits are calculated from other fields. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
370 lines
8 KiB
C
370 lines
8 KiB
C
/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
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*
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* Copyright (C) 2006 by OpenMoko, Inc.
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* Author: Harald Welte <laforge@openmoko.org>
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/sysdev.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/leds-gpio.h>
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#include <asm/plat-s3c/regs-serial.h>
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#include <asm/arch/fb.h>
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#include <asm/plat-s3c/nand.h>
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#include <asm/plat-s3c24xx/udc.h>
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#include <asm/arch/spi.h>
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#include <asm/arch/spi-gpio.h>
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#include <asm/plat-s3c24xx/common-smdk.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/plat-s3c24xx/pm.h>
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static struct map_desc qt2410_iodesc[] __initdata = {
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{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
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};
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#define UCON S3C2410_UCON_DEFAULT
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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}
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};
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/* LCD driver info */
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static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
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{
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/* Configuration for 640x480 SHARP LQ080V3DG01 */
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.lcdcon5 = S3C2410_LCDCON5_FRM565 |
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S3C2410_LCDCON5_INVVLINE |
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S3C2410_LCDCON5_INVVFRAME |
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S3C2410_LCDCON5_PWREN |
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S3C2410_LCDCON5_HWSWP,
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.pixclock = 40000, /* HCLK/4 */
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.xres = 640,
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.yres = 480,
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.bpp = 16,
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.left_margin = 44,
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.right_margin = 116,
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.hsync_len = 96,
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.upper_margin = 19,
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.lower_margin = 11,
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.vsync_len = 15,
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},
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{
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/* Configuration for 480x640 toppoly TD028TTEC1 */
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.lcdcon5 = S3C2410_LCDCON5_FRM565 |
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S3C2410_LCDCON5_INVVLINE |
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S3C2410_LCDCON5_INVVFRAME |
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S3C2410_LCDCON5_PWREN |
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S3C2410_LCDCON5_HWSWP,
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.type = S3C2410_LCDCON1_TFT,
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.width = 480,
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.height = 640,
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.pixclock = 40000, /* HCLK/4 */
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.xres = 480,
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.yres = 640,
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.bpp = 16,
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.left_margin = 8,
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.right_margin = 24,
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.hsync_len = 8,
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.upper_margin = 2,
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.lower_margin = 4,
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.vsync_len = 2,
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},
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{
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/* Config for 240x320 LCD */
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.lcdcon5 = S3C2410_LCDCON5_FRM565 |
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S3C2410_LCDCON5_INVVLINE |
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S3C2410_LCDCON5_INVVFRAME |
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S3C2410_LCDCON5_PWREN |
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S3C2410_LCDCON5_HWSWP,
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.type = S3C2410_LCDCON1_TFT,
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.width = 240,
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.height = 320,
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.pixclock = 100000, /* HCLK/10 */
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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.left_margin = 13,
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.right_margin = 8,
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.hsync_len = 4,
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.upper_margin = 2,
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.lower_margin = 7,
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.vsync_len = 4,
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},
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};
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static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
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.displays = qt2410_lcd_cfg,
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.num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
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.default_display = 0,
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.lpcsel = ((0xCE6) & ~7) | 1<<4,
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};
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/* CS8900 */
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static struct resource qt2410_cs89x0_resources[] = {
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[0] = {
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.start = 0x19000000,
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.end = 0x19000000 + 16,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_EINT9,
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.end = IRQ_EINT9,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device qt2410_cs89x0 = {
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.name = "cirrus-cs89x0",
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.num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
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.resource = qt2410_cs89x0_resources,
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};
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/* LED */
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static struct s3c24xx_led_platdata qt2410_pdata_led = {
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.gpio = S3C2410_GPB0,
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.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
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.name = "led",
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.def_trigger = "timer",
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};
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static struct platform_device qt2410_led = {
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.name = "s3c24xx_led",
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.id = 0,
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.dev = {
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.platform_data = &qt2410_pdata_led,
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},
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};
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/* SPI */
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static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
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{
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switch (cs) {
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case BITBANG_CS_ACTIVE:
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s3c2410_gpio_setpin(S3C2410_GPB5, 0);
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break;
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case BITBANG_CS_INACTIVE:
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s3c2410_gpio_setpin(S3C2410_GPB5, 1);
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break;
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}
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}
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static struct s3c2410_spigpio_info spi_gpio_cfg = {
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.pin_clk = S3C2410_GPG7,
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.pin_mosi = S3C2410_GPG6,
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.pin_miso = S3C2410_GPG5,
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.chip_select = &spi_gpio_cs,
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};
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static struct platform_device qt2410_spi = {
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.name = "s3c24xx-spi-gpio",
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.id = 1,
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.dev = {
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.platform_data = &spi_gpio_cfg,
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},
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};
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/* Board devices */
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static struct platform_device *qt2410_devices[] __initdata = {
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&s3c_device_usb,
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&s3c_device_lcd,
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&s3c_device_wdt,
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&s3c_device_i2c,
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&s3c_device_iis,
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&s3c_device_sdi,
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&s3c_device_usbgadget,
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&qt2410_spi,
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&qt2410_cs89x0,
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&qt2410_led,
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};
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static struct mtd_partition qt2410_nand_part[] = {
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[0] = {
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.name = "U-Boot",
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.size = 0x30000,
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.offset = 0,
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},
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[1] = {
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.name = "U-Boot environment",
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.offset = 0x30000,
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.size = 0x4000,
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},
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[2] = {
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.name = "kernel",
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.offset = 0x34000,
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.size = SZ_2M,
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},
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[3] = {
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.name = "initrd",
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.offset = 0x234000,
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.size = SZ_4M,
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},
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[4] = {
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.name = "jffs2",
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.offset = 0x634000,
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.size = 0x39cc000,
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},
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};
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static struct s3c2410_nand_set qt2410_nand_sets[] = {
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[0] = {
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.name = "NAND",
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.nr_chips = 1,
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.nr_partitions = ARRAY_SIZE(qt2410_nand_part),
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.partitions = qt2410_nand_part,
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},
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};
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/* choose a set of timings which should suit most 512Mbit
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* chips and beyond.
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*/
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static struct s3c2410_platform_nand qt2410_nand_info = {
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.tacls = 20,
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.twrph0 = 60,
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.twrph1 = 20,
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.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
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.sets = qt2410_nand_sets,
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};
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/* UDC */
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static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
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};
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static char tft_type = 's';
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static int __init qt2410_tft_setup(char *str)
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{
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tft_type = str[0];
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return 1;
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}
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__setup("tft=", qt2410_tft_setup);
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static void __init qt2410_map_io(void)
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{
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s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
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s3c24xx_init_clocks(12*1000*1000);
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s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
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}
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static void __init qt2410_machine_init(void)
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{
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s3c_device_nand.dev.platform_data = &qt2410_nand_info;
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switch (tft_type) {
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case 'p': /* production */
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qt2410_fb_info.default_display = 1;
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break;
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case 'b': /* big */
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qt2410_fb_info.default_display = 0;
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break;
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case 's': /* small */
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default:
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qt2410_fb_info.default_display = 2;
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break;
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}
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s3c24xx_fb_set_platdata(&qt2410_fb_info);
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s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
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s3c2410_gpio_setpin(S3C2410_GPB0, 1);
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s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
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s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
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platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
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s3c2410_pm_init();
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}
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MACHINE_START(QT2410, "QT2410")
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.phys_io = S3C2410_PA_UART,
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.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
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.boot_params = S3C2410_SDRAM_PA + 0x100,
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.map_io = qt2410_map_io,
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.init_irq = s3c24xx_init_irq,
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.init_machine = qt2410_machine_init,
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.timer = &s3c24xx_timer,
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MACHINE_END
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