32dc80c9cb
This patch adds basic mach support for the mx2 processor family, based on the original freescale code and adapted to mainline kernel coding style. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
77 lines
2.9 KiB
C
77 lines
2.9 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_MXC_IIM_H__
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#define __ASM_ARCH_MXC_IIM_H__
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/* Register offsets */
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#define MXC_IIMSTAT 0x0000
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#define MXC_IIMSTATM 0x0004
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#define MXC_IIMERR 0x0008
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#define MXC_IIMEMASK 0x000C
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#define MXC_IIMFCTL 0x0010
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#define MXC_IIMUA 0x0014
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#define MXC_IIMLA 0x0018
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#define MXC_IIMSDAT 0x001C
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#define MXC_IIMPREV 0x0020
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#define MXC_IIMSREV 0x0024
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#define MXC_IIMPRG_P 0x0028
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#define MXC_IIMSCS0 0x002C
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#define MXC_IIMSCS1 0x0030
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#define MXC_IIMSCS2 0x0034
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#define MXC_IIMSCS3 0x0038
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#define MXC_IIMFBAC0 0x0800
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#define MXC_IIMJAC 0x0804
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#define MXC_IIMHWV1 0x0808
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#define MXC_IIMHWV2 0x080C
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#define MXC_IIMHAB0 0x0810
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#define MXC_IIMHAB1 0x0814
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/* Definitions for i.MX27 TO2 */
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#define MXC_IIMMAC 0x0814
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#define MXC_IIMPREV_FUSE 0x0818
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#define MXC_IIMSREV_FUSE 0x081C
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#define MXC_IIMSJC_CHALL_0 0x0820
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#define MXC_IIMSJC_CHALL_7 0x083C
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#define MXC_IIMFB0UC17 0x0840
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#define MXC_IIMFB0UC255 0x0BFC
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#define MXC_IIMFBAC1 0x0C00
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/* Definitions for i.MX27 TO2 */
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#define MXC_IIMSUID 0x0C04
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#define MXC_IIMKEY0 0x0C04
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#define MXC_IIMKEY20 0x0C54
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#define MXC_IIMSJC_RESP_0 0x0C58
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#define MXC_IIMSJC_RESP_7 0x0C74
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#define MXC_IIMFB1UC30 0x0C78
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#define MXC_IIMFB1UC255 0x0FFC
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/* Bit definitions */
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#define MXC_IIMHWV1_WLOCK (0x1 << 7)
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#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6)
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#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5)
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#define MXC_IIMHWV1_BOOT_INT (0x1 << 4)
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#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3)
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#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2)
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#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1)
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#define MXC_IIMHWV2_WLOCK (0x1 << 7)
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#define MXC_IIMHWV2_BP_SDMA (0x1 << 6)
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#define MXC_IIMHWV2_SCM_DCM (0x1 << 5)
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#endif /* __ASM_ARCH_MXC_IIM_H__ */
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