e8edc6e03a
First thing mm.h does is including sched.h solely for can_do_mlock() inline function which has "current" dereference inside. By dealing with can_do_mlock() mm.h can be detached from sched.h which is good. See below, why. This patch a) removes unconditional inclusion of sched.h from mm.h b) makes can_do_mlock() normal function in mm/mlock.c c) exports can_do_mlock() to not break compilation d) adds sched.h inclusions back to files that were getting it indirectly. e) adds less bloated headers to some files (asm/signal.h, jiffies.h) that were getting them indirectly Net result is: a) mm.h users would get less code to open, read, preprocess, parse, ... if they don't need sched.h b) sched.h stops being dependency for significant number of files: on x86_64 allmodconfig touching sched.h results in recompile of 4083 files, after patch it's only 3744 (-8.3%). Cross-compile tested on all arm defconfigs, all mips defconfigs, all powerpc defconfigs, alpha alpha-up arm i386 i386-up i386-defconfig i386-allnoconfig ia64 ia64-up m68k mips parisc parisc-up powerpc powerpc-up s390 s390-up sparc sparc-up sparc64 sparc64-up um-x86_64 x86_64 x86_64-up x86_64-defconfig x86_64-allnoconfig as well as my two usual configs. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
548 lines
13 KiB
C
548 lines
13 KiB
C
/*
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* Handle unaligned accesses by emulation.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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*
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* This file contains exception handler for address error exception with the
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* special capability to execute faulting instructions in software. The
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* handler does not try to handle the case when the program counter points
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* to an address not aligned to a word boundary.
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*
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* Putting data to unaligned addresses is a bad practice even on Intel where
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* only the performance is affected. Much worse is that such code is non-
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* portable. Due to several programs that die on MIPS due to alignment
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* problems I decided to implement this handler anyway though I originally
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* didn't intend to do this at all for user code.
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*
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* For now I enable fixing of address errors by default to make life easier.
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* I however intend to disable this somewhen in the future when the alignment
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* problems with user programs have been fixed. For programmers this is the
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* right way to go.
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*
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* Fixing address errors is a per process option. The option is inherited
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* across fork(2) and execve(2) calls. If you really want to use the
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* option in your user programs - I discourage the use of the software
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* emulation strongly - use the following code in your userland stuff:
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*
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* #include <sys/sysmips.h>
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*
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* ...
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* sysmips(MIPS_FIXADE, x);
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* ...
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*
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* The argument x is 0 for disabling software emulation, enabled otherwise.
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*
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* Below a little program to play around with this feature.
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*
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* #include <stdio.h>
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* #include <sys/sysmips.h>
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*
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* struct foo {
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* unsigned char bar[8];
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* };
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*
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* main(int argc, char *argv[])
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* {
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* struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
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* unsigned int *p = (unsigned int *) (x.bar + 3);
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* int i;
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*
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* if (argc > 1)
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* sysmips(MIPS_FIXADE, atoi(argv[1]));
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*
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* printf("*p = %08lx\n", *p);
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*
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* *p = 0xdeadface;
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*
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* for(i = 0; i <= 7; i++)
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* printf("%02x ", x.bar[i]);
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* printf("\n");
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* }
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*
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* Coprocessor loads are not supported; I think this case is unimportant
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* in the practice.
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*
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* TODO: Handle ndc (attempted store to doubleword in uncached memory)
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* exception for the R6000.
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* A store crossing a page boundary might be executed only partially.
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* Undo the partial store in this case.
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*/
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/smp.h>
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#include <linux/sched.h>
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#include <asm/asm.h>
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#include <asm/branch.h>
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#include <asm/byteorder.h>
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#include <asm/inst.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#define STR(x) __STR(x)
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#define __STR(x) #x
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#ifdef CONFIG_PROC_FS
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unsigned long unaligned_instructions;
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#endif
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static inline int emulate_load_store_insn(struct pt_regs *regs,
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void __user *addr, unsigned int __user *pc,
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unsigned long **regptr, unsigned long *newvalue)
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{
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union mips_instruction insn;
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unsigned long value;
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unsigned int res;
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regs->regs[0] = 0;
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*regptr=NULL;
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/*
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* This load never faults.
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*/
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__get_user(insn.word, pc);
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switch (insn.i_format.opcode) {
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/*
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* These are instructions that a compiler doesn't generate. We
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* can assume therefore that the code is MIPS-aware and
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* really buggy. Emulating these instructions would break the
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* semantics anyway.
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*/
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case ll_op:
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case lld_op:
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case sc_op:
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case scd_op:
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/*
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* For these instructions the only way to create an address
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* error is an attempted access to kernel/supervisor address
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* space.
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*/
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case ldl_op:
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case ldr_op:
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case lwl_op:
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case lwr_op:
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case sdl_op:
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case sdr_op:
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case swl_op:
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case swr_op:
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case lb_op:
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case lbu_op:
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case sb_op:
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goto sigbus;
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/*
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* The remaining opcodes are the ones that are really of interest.
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*/
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case lh_op:
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if (!access_ok(VERIFY_READ, addr, 2))
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goto sigbus;
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__asm__ __volatile__ (".set\tnoat\n"
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#ifdef __BIG_ENDIAN
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"1:\tlb\t%0, 0(%2)\n"
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"2:\tlbu\t$1, 1(%2)\n\t"
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#endif
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#ifdef __LITTLE_ENDIAN
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"1:\tlb\t%0, 1(%2)\n"
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"2:\tlbu\t$1, 0(%2)\n\t"
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#endif
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"sll\t%0, 0x8\n\t"
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"or\t%0, $1\n\t"
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"li\t%1, 0\n"
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"3:\t.set\tat\n\t"
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".section\t.fixup,\"ax\"\n\t"
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"4:\tli\t%1, %3\n\t"
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"j\t3b\n\t"
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".previous\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b, 4b\n\t"
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STR(PTR)"\t2b, 4b\n\t"
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".previous"
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: "=&r" (value), "=r" (res)
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: "r" (addr), "i" (-EFAULT));
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if (res)
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goto fault;
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*newvalue = value;
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*regptr = ®s->regs[insn.i_format.rt];
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break;
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case lw_op:
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if (!access_ok(VERIFY_READ, addr, 4))
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goto sigbus;
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tlwl\t%0, (%2)\n"
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"2:\tlwr\t%0, 3(%2)\n\t"
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#endif
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#ifdef __LITTLE_ENDIAN
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"1:\tlwl\t%0, 3(%2)\n"
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"2:\tlwr\t%0, (%2)\n\t"
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#endif
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"li\t%1, 0\n"
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"3:\t.section\t.fixup,\"ax\"\n\t"
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"4:\tli\t%1, %3\n\t"
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"j\t3b\n\t"
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".previous\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b, 4b\n\t"
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STR(PTR)"\t2b, 4b\n\t"
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".previous"
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: "=&r" (value), "=r" (res)
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: "r" (addr), "i" (-EFAULT));
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if (res)
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goto fault;
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*newvalue = value;
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*regptr = ®s->regs[insn.i_format.rt];
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break;
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case lhu_op:
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if (!access_ok(VERIFY_READ, addr, 2))
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goto sigbus;
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__asm__ __volatile__ (
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".set\tnoat\n"
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#ifdef __BIG_ENDIAN
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"1:\tlbu\t%0, 0(%2)\n"
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"2:\tlbu\t$1, 1(%2)\n\t"
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#endif
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#ifdef __LITTLE_ENDIAN
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"1:\tlbu\t%0, 1(%2)\n"
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"2:\tlbu\t$1, 0(%2)\n\t"
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#endif
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"sll\t%0, 0x8\n\t"
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"or\t%0, $1\n\t"
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"li\t%1, 0\n"
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"3:\t.set\tat\n\t"
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".section\t.fixup,\"ax\"\n\t"
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"4:\tli\t%1, %3\n\t"
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"j\t3b\n\t"
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".previous\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b, 4b\n\t"
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STR(PTR)"\t2b, 4b\n\t"
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".previous"
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: "=&r" (value), "=r" (res)
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: "r" (addr), "i" (-EFAULT));
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if (res)
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goto fault;
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*newvalue = value;
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*regptr = ®s->regs[insn.i_format.rt];
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break;
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case lwu_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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* if we're on a 32-bit processor and an i-cache incoherency
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* or race makes us see a 64-bit instruction here the sdl/sdr
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* would blow up, so for now we don't handle unaligned 64-bit
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* instructions on 32-bit kernels.
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*/
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if (!access_ok(VERIFY_READ, addr, 4))
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goto sigbus;
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tlwl\t%0, (%2)\n"
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"2:\tlwr\t%0, 3(%2)\n\t"
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#endif
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#ifdef __LITTLE_ENDIAN
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"1:\tlwl\t%0, 3(%2)\n"
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"2:\tlwr\t%0, (%2)\n\t"
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#endif
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"dsll\t%0, %0, 32\n\t"
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"dsrl\t%0, %0, 32\n\t"
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"li\t%1, 0\n"
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"3:\t.section\t.fixup,\"ax\"\n\t"
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"4:\tli\t%1, %3\n\t"
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"j\t3b\n\t"
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".previous\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b, 4b\n\t"
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STR(PTR)"\t2b, 4b\n\t"
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".previous"
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: "=&r" (value), "=r" (res)
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: "r" (addr), "i" (-EFAULT));
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if (res)
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goto fault;
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*newvalue = value;
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*regptr = ®s->regs[insn.i_format.rt];
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break;
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#endif /* CONFIG_64BIT */
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/* Cannot handle 64-bit instructions in 32-bit kernel */
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goto sigill;
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case ld_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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* if we're on a 32-bit processor and an i-cache incoherency
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* or race makes us see a 64-bit instruction here the sdl/sdr
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* would blow up, so for now we don't handle unaligned 64-bit
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* instructions on 32-bit kernels.
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*/
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if (!access_ok(VERIFY_READ, addr, 8))
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goto sigbus;
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tldl\t%0, (%2)\n"
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"2:\tldr\t%0, 7(%2)\n\t"
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#endif
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#ifdef __LITTLE_ENDIAN
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"1:\tldl\t%0, 7(%2)\n"
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"2:\tldr\t%0, (%2)\n\t"
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#endif
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"li\t%1, 0\n"
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"3:\t.section\t.fixup,\"ax\"\n\t"
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"4:\tli\t%1, %3\n\t"
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"j\t3b\n\t"
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".previous\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b, 4b\n\t"
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STR(PTR)"\t2b, 4b\n\t"
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".previous"
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: "=&r" (value), "=r" (res)
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: "r" (addr), "i" (-EFAULT));
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if (res)
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goto fault;
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*newvalue = value;
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*regptr = ®s->regs[insn.i_format.rt];
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break;
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#endif /* CONFIG_64BIT */
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/* Cannot handle 64-bit instructions in 32-bit kernel */
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goto sigill;
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case sh_op:
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if (!access_ok(VERIFY_WRITE, addr, 2))
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goto sigbus;
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value = regs->regs[insn.i_format.rt];
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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".set\tnoat\n"
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"1:\tsb\t%1, 1(%2)\n\t"
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"srl\t$1, %1, 0x8\n"
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"2:\tsb\t$1, 0(%2)\n\t"
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".set\tat\n\t"
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#endif
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#ifdef __LITTLE_ENDIAN
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".set\tnoat\n"
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"1:\tsb\t%1, 0(%2)\n\t"
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"srl\t$1,%1, 0x8\n"
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"2:\tsb\t$1, 1(%2)\n\t"
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".set\tat\n\t"
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#endif
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"li\t%0, 0\n"
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"3:\n\t"
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".section\t.fixup,\"ax\"\n\t"
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"4:\tli\t%0, %3\n\t"
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"j\t3b\n\t"
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".previous\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b, 4b\n\t"
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STR(PTR)"\t2b, 4b\n\t"
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".previous"
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: "=r" (res)
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: "r" (value), "r" (addr), "i" (-EFAULT));
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if (res)
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goto fault;
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break;
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case sw_op:
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if (!access_ok(VERIFY_WRITE, addr, 4))
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goto sigbus;
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value = regs->regs[insn.i_format.rt];
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tswl\t%1,(%2)\n"
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"2:\tswr\t%1, 3(%2)\n\t"
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#endif
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#ifdef __LITTLE_ENDIAN
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"1:\tswl\t%1, 3(%2)\n"
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"2:\tswr\t%1, (%2)\n\t"
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#endif
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"li\t%0, 0\n"
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"3:\n\t"
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".section\t.fixup,\"ax\"\n\t"
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"4:\tli\t%0, %3\n\t"
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"j\t3b\n\t"
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".previous\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b, 4b\n\t"
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STR(PTR)"\t2b, 4b\n\t"
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".previous"
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: "=r" (res)
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: "r" (value), "r" (addr), "i" (-EFAULT));
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if (res)
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goto fault;
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break;
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case sd_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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|
* if we're on a 32-bit processor and an i-cache incoherency
|
|
* or race makes us see a 64-bit instruction here the sdl/sdr
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|
* would blow up, so for now we don't handle unaligned 64-bit
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* instructions on 32-bit kernels.
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*/
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if (!access_ok(VERIFY_WRITE, addr, 8))
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goto sigbus;
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|
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value = regs->regs[insn.i_format.rt];
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__asm__ __volatile__ (
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|
#ifdef __BIG_ENDIAN
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|
"1:\tsdl\t%1,(%2)\n"
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|
"2:\tsdr\t%1, 7(%2)\n\t"
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|
#endif
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|
#ifdef __LITTLE_ENDIAN
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|
"1:\tsdl\t%1, 7(%2)\n"
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|
"2:\tsdr\t%1, (%2)\n\t"
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|
#endif
|
|
"li\t%0, 0\n"
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|
"3:\n\t"
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|
".section\t.fixup,\"ax\"\n\t"
|
|
"4:\tli\t%0, %3\n\t"
|
|
"j\t3b\n\t"
|
|
".previous\n\t"
|
|
".section\t__ex_table,\"a\"\n\t"
|
|
STR(PTR)"\t1b, 4b\n\t"
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|
STR(PTR)"\t2b, 4b\n\t"
|
|
".previous"
|
|
: "=r" (res)
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|
: "r" (value), "r" (addr), "i" (-EFAULT));
|
|
if (res)
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|
goto fault;
|
|
break;
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
/* Cannot handle 64-bit instructions in 32-bit kernel */
|
|
goto sigill;
|
|
|
|
case lwc1_op:
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|
case ldc1_op:
|
|
case swc1_op:
|
|
case sdc1_op:
|
|
/*
|
|
* I herewith declare: this does not happen. So send SIGBUS.
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|
*/
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|
goto sigbus;
|
|
|
|
case lwc2_op:
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|
case ldc2_op:
|
|
case swc2_op:
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case sdc2_op:
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/*
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|
* These are the coprocessor 2 load/stores. The current
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* implementations don't use cp2 and cp2 should always be
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* disabled in c0_status. So send SIGILL.
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|
* (No longer true: The Sony Praystation uses cp2 for
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* 3D matrix operations. Dunno if that thingy has a MMU ...)
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*/
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|
default:
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/*
|
|
* Pheeee... We encountered an yet unknown instruction or
|
|
* cache coherence problem. Die sucker, die ...
|
|
*/
|
|
goto sigill;
|
|
}
|
|
|
|
#ifdef CONFIG_PROC_FS
|
|
unaligned_instructions++;
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
fault:
|
|
/* Did we have an exception handler installed? */
|
|
if (fixup_exception(regs))
|
|
return 1;
|
|
|
|
die_if_kernel ("Unhandled kernel unaligned access", regs);
|
|
send_sig(SIGSEGV, current, 1);
|
|
|
|
return 0;
|
|
|
|
sigbus:
|
|
die_if_kernel("Unhandled kernel unaligned access", regs);
|
|
send_sig(SIGBUS, current, 1);
|
|
|
|
return 0;
|
|
|
|
sigill:
|
|
die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
|
|
send_sig(SIGILL, current, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
asmlinkage void do_ade(struct pt_regs *regs)
|
|
{
|
|
unsigned long *regptr, newval;
|
|
extern int do_dsemulret(struct pt_regs *);
|
|
unsigned int __user *pc;
|
|
mm_segment_t seg;
|
|
|
|
/*
|
|
* Address errors may be deliberately induced by the FPU emulator to
|
|
* retake control of the CPU after executing the instruction in the
|
|
* delay slot of an emulated branch.
|
|
*/
|
|
/* Terminate if exception was recognized as a delay slot return */
|
|
if (do_dsemulret(regs))
|
|
return;
|
|
|
|
/* Otherwise handle as normal */
|
|
|
|
/*
|
|
* Did we catch a fault trying to load an instruction?
|
|
* Or are we running in MIPS16 mode?
|
|
*/
|
|
if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1))
|
|
goto sigbus;
|
|
|
|
pc = (unsigned int __user *) exception_epc(regs);
|
|
if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0)
|
|
goto sigbus;
|
|
|
|
/*
|
|
* Do branch emulation only if we didn't forward the exception.
|
|
* This is all so but ugly ...
|
|
*/
|
|
seg = get_fs();
|
|
if (!user_mode(regs))
|
|
set_fs(KERNEL_DS);
|
|
if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc,
|
|
®ptr, &newval)) {
|
|
compute_return_epc(regs);
|
|
/*
|
|
* Now that branch is evaluated, update the dest
|
|
* register if necessary
|
|
*/
|
|
if (regptr)
|
|
*regptr = newval;
|
|
}
|
|
set_fs(seg);
|
|
|
|
return;
|
|
|
|
sigbus:
|
|
die_if_kernel("Kernel unaligned instruction access", regs);
|
|
force_sig(SIGBUS, current);
|
|
|
|
/*
|
|
* XXX On return from the signal handler we should advance the epc
|
|
*/
|
|
}
|