91f6a589fb
Patch from Lennert Buytenhek All ixdp platforms currently have a cpld mapped in at 0xfafff000. Since this address is not 1M-aligned, a regular page mapping will be used instead of a section mapping, which opens up the possibility of triggering ixp2400 erratum #66 as we only do the XCB=101 workaround thing for section mappings. There is still a lot of space higher up in the virtual memory map for 1M mappings, so move the cpld mapping to 0xfe000000 and make it 1M big so that a section mapping will be used for it. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
57 lines
2 KiB
C
57 lines
2 KiB
C
/*
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* include/asm-arm/arch-ixp2000/ixdp2x01.h
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*
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* Platform definitions for IXDP2X01 && IXDP2801 systems
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2004 (c) MontaVista Software, Inc.
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*
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* Based on original code Copyright (c) 2002-2003 Intel Corporation
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __IXDP2X01_H__
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#define __IXDP2X01_H__
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#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
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#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000
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#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
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#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
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#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
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#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
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#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
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#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60)
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#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60)
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#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80)
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#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16)
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#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00)
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#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08)
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#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C)
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#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10)
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#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG
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#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14)
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#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20)
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#define IXDP2X01_CPLD_FLASH_INTERN 0x8000
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#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF
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#define IXDP2X01_FLASH_WINDOW_BITS 25
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#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS)
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#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1)
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#define IXDP2X01_UART_CLK 1843200
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#define IXDP2X01_GPIO_I2C_ENABLE 0x02
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#define IXDP2X01_GPIO_SCL 0x07
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#define IXDP2X01_GPIO_SDA 0x06
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#endif /* __IXDP2x01_H__ */
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