95872f427e
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are clock gated and SDRAM in self-refresh mode. That means the low level LP1 suspending and resuming code couldn't be run on DRAM and the CPU must switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. The LP1 low level handling code need to be moved to IRAM area first. And marking the LP1 mask for indicating the Tegra device is in LP1. The CPU power timer needs to be re-calculated based on 32KHz that was originally based on PCLK. When resuming from LP1, the LP1 reset handler will resume PLLs and then put DRAM to normal mode. Then jumping to the "tegra_resume" that will restore full context before back to kernel. The "tegra_resume" handler was expected to be found in PMC_SCRATCH41 register. This is common LP1 procedures for Tegra, so we do these jobs mainly in this patch: * moving LP1 low level handling code to IRAM * marking LP1 mask * copying the physical address of "tegra_resume" to PMC_SCRATCH41 * re-calculate the CPU power timer based on 32KHz Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)] Signed-off-by: Stephen Warren <swarren@nvidia.com>
44 lines
1.4 KiB
C
44 lines
1.4 KiB
C
/*
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef __MACH_TEGRA_PMC_H
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#define __MACH_TEGRA_PMC_H
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enum tegra_suspend_mode {
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TEGRA_SUSPEND_NONE = 0,
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TEGRA_SUSPEND_LP2, /* CPU voltage off */
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TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
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TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
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TEGRA_MAX_SUSPEND_MODE,
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};
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#ifdef CONFIG_PM_SLEEP
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enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
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void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
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void tegra_pmc_suspend(void);
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void tegra_pmc_resume(void);
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void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
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void tegra_pmc_suspend_init(void);
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#endif
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bool tegra_pmc_cpu_is_powered(int cpuid);
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int tegra_pmc_cpu_power_on(int cpuid);
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int tegra_pmc_cpu_remove_clamping(int cpuid);
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void tegra_pmc_init(void);
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#endif
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