984ca29501
Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
177 lines
6 KiB
C
177 lines
6 KiB
C
/*
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* r8a73a4 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a73a4.h>
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#include <asm/mach/arch.h>
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#define SCIF_COMMON(scif_type, baseaddr, irq) \
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.type = scif_type, \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.irqs = SCIx_IRQ_MUXED(irq)
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#define SCIFA_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
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}
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#define SCIFB_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
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static const struct plat_sci_port scif[] = {
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SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
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SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
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SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
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SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
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SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
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SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
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};
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static inline void r8a73a4_register_scif(int idx)
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{
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platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
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sizeof(struct plat_sci_port));
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}
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static const struct renesas_irqc_config irqc0_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
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};
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static const struct resource irqc0_resources[] = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
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DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
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DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
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DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
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DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
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DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
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DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
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DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
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DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
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DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
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DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
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DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
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DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
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DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
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DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
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DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
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DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
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DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
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DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
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DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
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DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
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DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
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DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
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DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
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DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
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DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
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DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
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DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
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};
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static const struct renesas_irqc_config irqc1_data = {
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.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
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};
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static const struct resource irqc1_resources[] = {
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DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
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DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
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DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
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DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
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DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
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DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
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DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
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DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
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DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
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DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
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DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
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DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
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DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
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DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
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DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
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DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
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DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
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DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
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DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
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DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
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DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
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DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
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DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
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DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
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DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
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DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
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DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
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};
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#define r8a73a4_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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void __init r8a73a4_add_standard_devices(void)
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{
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r8a73a4_register_scif(SCIFA0);
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r8a73a4_register_scif(SCIFA1);
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r8a73a4_register_scif(SCIFB0);
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r8a73a4_register_scif(SCIFB1);
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r8a73a4_register_scif(SCIFB2);
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r8a73a4_register_scif(SCIFB3);
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r8a73a4_register_irqc(0);
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r8a73a4_register_irqc(1);
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}
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#ifdef CONFIG_USE_OF
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void __init r8a73a4_add_standard_devices_dt(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char *r8a73a4_boards_compat_dt[] __initdata = {
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"renesas,r8a73a4",
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NULL,
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};
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DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
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.init_irq = irqchip_init,
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.init_machine = r8a73a4_add_standard_devices_dt,
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.init_time = shmobile_timer_init,
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.dt_compat = r8a73a4_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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