0ecdca26e5
This results in smaller/faster/simpler code and allows future optimizations.
Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}.
v2:
* updated for scc_pata
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
380 lines
10 KiB
C
380 lines
10 KiB
C
/*
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* linux/drivers/ide/pci/cs5530.c Version 0.7 Sept 10, 2002
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*
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* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
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* Ditto of GNU General Public License.
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*
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* Copyright (C) 2000 Mark Lord <mlord@pobox.com>
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* May be copied or modified under the terms of the GNU General Public License
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*
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* Development of this chipset driver was funded
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* by the nice folks at National Semiconductor.
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*
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* Documentation:
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* CS5530 documentation available from National Semiconductor.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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/**
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* cs5530_xfer_set_mode - set a new transfer mode at the drive
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* @drive: drive to tune
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* @mode: new mode
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*
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* Logging wrapper to the IDE driver speed configuration. This can
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* probably go away now.
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*/
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static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
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{
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printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
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drive->name, ide_xfer_verbose(mode));
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return (ide_config_drive_speed(drive, mode));
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}
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/*
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* Here are the standard PIO mode 0-4 timings for each "format".
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* Format-0 uses fast data reg timings, with slower command reg timings.
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* Format-1 uses fast timings for all registers, but won't work with all drives.
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*/
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static unsigned int cs5530_pio_timings[2][5] = {
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{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
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{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
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};
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/*
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* After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
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*/
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#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
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#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
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/**
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* cs5530_tuneproc - select/set PIO modes
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*
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* cs5530_tuneproc() handles selection/setting of PIO modes
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* for both the chipset and drive.
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*
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* The ide_init_cs5530() routine guarantees that all drives
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* will have valid default PIO timings set up before we get here.
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*/
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static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autotune" */
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{
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ide_hwif_t *hwif = HWIF(drive);
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unsigned int format;
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unsigned long basereg = CS5530_BASEREG(hwif);
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static u8 modes[5] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
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pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
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if (!cs5530_set_xfer_mode(drive, modes[pio])) {
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format = (inl(basereg + 4) >> 31) & 1;
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outl(cs5530_pio_timings[format][pio],
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basereg+(drive->select.b.unit<<3));
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}
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}
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/**
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* cs5530_config_dma - select/set DMA and UDMA modes
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* @drive: drive to tune
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*
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* cs5530_config_dma() handles selection/setting of DMA/UDMA modes
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* for both the chipset and drive. The CS5530 has limitations about
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* mixing DMA/UDMA on the same cable.
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*/
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static int cs5530_config_dma (ide_drive_t *drive)
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{
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int udma_ok = 1, mode = 0;
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ide_hwif_t *hwif = HWIF(drive);
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int unit = drive->select.b.unit;
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ide_drive_t *mate = &hwif->drives[unit^1];
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struct hd_driveid *id = drive->id;
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unsigned int reg, timings = 0;
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unsigned long basereg;
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/*
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* Default to DMA-off in case we run into trouble here.
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*/
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hwif->ide_dma_off_quietly(drive);
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/*
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* The CS5530 specifies that two drives sharing a cable cannot
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* mix UDMA/MDMA. It has to be one or the other, for the pair,
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* though different timings can still be chosen for each drive.
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* We could set the appropriate timing bits on the fly,
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* but that might be a bit confusing. So, for now we statically
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* handle this requirement by looking at our mate drive to see
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* what it is capable of, before choosing a mode for our own drive.
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*
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* Note: This relies on the fact we never fail from UDMA to MWDMA_2
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* but instead drop to PIO
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*/
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if (mate->present) {
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struct hd_driveid *mateid = mate->id;
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if (mateid && (mateid->capability & 1) &&
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!__ide_dma_bad_drive(mate)) {
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if ((mateid->field_valid & 4) &&
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(mateid->dma_ultra & 7))
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udma_ok = 1;
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else if ((mateid->field_valid & 2) &&
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(mateid->dma_mword & 7))
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udma_ok = 0;
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else
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udma_ok = 1;
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}
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}
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/*
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* Now see what the current drive is capable of,
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* selecting UDMA only if the mate said it was ok.
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*/
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if (id && (id->capability & 1) && drive->autodma &&
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!__ide_dma_bad_drive(drive)) {
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if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
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if (id->dma_ultra & 4)
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mode = XFER_UDMA_2;
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else if (id->dma_ultra & 2)
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mode = XFER_UDMA_1;
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else if (id->dma_ultra & 1)
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mode = XFER_UDMA_0;
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}
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if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
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if (id->dma_mword & 4)
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mode = XFER_MW_DMA_2;
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else if (id->dma_mword & 2)
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mode = XFER_MW_DMA_1;
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else if (id->dma_mword & 1)
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mode = XFER_MW_DMA_0;
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}
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}
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/*
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* Tell the drive to switch to the new mode; abort on failure.
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*/
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if (!mode || cs5530_set_xfer_mode(drive, mode))
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return 1; /* failure */
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/*
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* Now tune the chipset to match the drive:
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*/
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switch (mode) {
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case XFER_UDMA_0: timings = 0x00921250; break;
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case XFER_UDMA_1: timings = 0x00911140; break;
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case XFER_UDMA_2: timings = 0x00911030; break;
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case XFER_MW_DMA_0: timings = 0x00077771; break;
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case XFER_MW_DMA_1: timings = 0x00012121; break;
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case XFER_MW_DMA_2: timings = 0x00002020; break;
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default:
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BUG();
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break;
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}
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basereg = CS5530_BASEREG(hwif);
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reg = inl(basereg + 4); /* get drive0 config register */
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timings |= reg & 0x80000000; /* preserve PIO format bit */
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if (unit == 0) { /* are we configuring drive0? */
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outl(timings, basereg + 4); /* write drive0 config register */
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} else {
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if (timings & 0x00100000)
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reg |= 0x00100000; /* enable UDMA timings for both drives */
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else
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reg &= ~0x00100000; /* disable UDMA timings for both drives */
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outl(reg, basereg + 4); /* write drive0 config register */
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outl(timings, basereg + 12); /* write drive1 config register */
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}
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/*
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* Finally, turn DMA on in software, and exit.
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*/
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return hwif->ide_dma_on(drive); /* success */
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}
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/**
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* init_chipset_5530 - set up 5530 bridge
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* @dev: PCI device
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* @name: device name
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*
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* Initialize the cs5530 bridge for reliable IDE DMA operation.
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*/
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static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
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{
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struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
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unsigned long flags;
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dev = NULL;
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while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
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switch (dev->device) {
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case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
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master_0 = pci_dev_get(dev);
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break;
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case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
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cs5530_0 = pci_dev_get(dev);
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break;
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}
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}
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if (!master_0) {
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printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
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goto out;
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}
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if (!cs5530_0) {
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printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
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goto out;
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}
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spin_lock_irqsave(&ide_lock, flags);
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/* all CPUs (there should only be one CPU with this chipset) */
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/*
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* Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
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* --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
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*/
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pci_set_master(cs5530_0);
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pci_set_mwi(cs5530_0);
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/*
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* Set PCI CacheLineSize to 16-bytes:
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* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
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*/
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pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
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/*
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* Disable trapping of UDMA register accesses (Win98 hack):
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* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
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*/
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pci_write_config_word(cs5530_0, 0xd0, 0x5006);
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/*
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* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
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* The other settings are what is necessary to get the register
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* into a sane state for IDE DMA operation.
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*/
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pci_write_config_byte(master_0, 0x40, 0x1e);
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/*
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* Set max PCI burst size (16-bytes seems to work best):
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* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
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* all others: clear bit-1 at 0x41, and do:
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* 128bytes: OR 0x00 at 0x41
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* 256bytes: OR 0x04 at 0x41
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* 512bytes: OR 0x08 at 0x41
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* 1024bytes: OR 0x0c at 0x41
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*/
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pci_write_config_byte(master_0, 0x41, 0x14);
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/*
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* These settings are necessary to get the chip
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* into a sane state for IDE DMA operation.
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*/
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pci_write_config_byte(master_0, 0x42, 0x00);
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pci_write_config_byte(master_0, 0x43, 0xc1);
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spin_unlock_irqrestore(&ide_lock, flags);
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out:
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pci_dev_put(master_0);
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pci_dev_put(cs5530_0);
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return 0;
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}
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/**
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* init_hwif_cs5530 - initialise an IDE channel
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* @hwif: IDE to initialize
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*
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* This gets invoked by the IDE driver once for each channel. It
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* performs channel-specific pre-initialization before drive probing.
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*/
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static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
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{
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unsigned long basereg;
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u32 d0_timings;
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hwif->autodma = 0;
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if (hwif->mate)
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hwif->serialized = hwif->mate->serialized = 1;
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hwif->tuneproc = &cs5530_tuneproc;
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basereg = CS5530_BASEREG(hwif);
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d0_timings = inl(basereg + 0);
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if (CS5530_BAD_PIO(d0_timings)) {
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/* PIO timings not initialized? */
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outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
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if (!hwif->drives[0].autotune)
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hwif->drives[0].autotune = 1;
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/* needs autotuning later */
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}
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if (CS5530_BAD_PIO(inl(basereg + 8))) {
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/* PIO timings not initialized? */
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outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
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if (!hwif->drives[1].autotune)
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hwif->drives[1].autotune = 1;
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/* needs autotuning later */
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}
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hwif->atapi_dma = 1;
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hwif->ultra_mask = 0x07;
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hwif->mwdma_mask = 0x07;
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hwif->ide_dma_check = &cs5530_config_dma;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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}
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static ide_pci_device_t cs5530_chipset __devinitdata = {
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.name = "CS5530",
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.init_chipset = init_chipset_cs5530,
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.init_hwif = init_hwif_cs5530,
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.channels = 2,
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.autodma = AUTODMA,
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.bootable = ON_BOARD,
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};
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static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &cs5530_chipset);
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}
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static struct pci_device_id cs5530_pci_tbl[] = {
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
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static struct pci_driver driver = {
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.name = "CS5530 IDE",
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.id_table = cs5530_pci_tbl,
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.probe = cs5530_init_one,
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};
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static int __init cs5530_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(cs5530_ide_init);
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MODULE_AUTHOR("Mark Lord");
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MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
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MODULE_LICENSE("GPL");
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