a0663a79ad
The context allocation scheme we use depends upon there being a 1<-->1 mapping from cpu to physical TLB for correctness. Chips like Niagara break this assumption. So what we do is notify all cpus with a cross call when the context version number changes, and if necessary this makes them allocate a valid context for the address space they are running at the time. Stress tested with make -j1024, make -j2048, and make -j4096 kernel builds on a 32-strand, 8 core, T2000 with 16GB of ram. Signed-off-by: David S. Miller <davem@davemloft.net>
121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
/* $Id: mmu_context.h,v 1.54 2002/02/09 19:49:31 davem Exp $ */
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#ifndef __SPARC64_MMU_CONTEXT_H
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#define __SPARC64_MMU_CONTEXT_H
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/* Derived heavily from Linus's Alpha/AXP ASN code... */
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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#include <asm/system.h>
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#include <asm/spitfire.h>
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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extern spinlock_t ctx_alloc_lock;
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extern unsigned long tlb_context_cache;
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extern unsigned long mmu_context_bmap[];
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extern void get_new_mmu_context(struct mm_struct *mm);
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#ifdef CONFIG_SMP
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extern void smp_new_mmu_context_version(void);
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#else
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#define smp_new_mmu_context_version() do { } while (0)
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#endif
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extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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extern void destroy_context(struct mm_struct *mm);
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extern void __tsb_context_switch(unsigned long pgd_pa,
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unsigned long tsb_reg,
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unsigned long tsb_vaddr,
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unsigned long tsb_pte,
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unsigned long tsb_descr_pa);
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static inline void tsb_context_switch(struct mm_struct *mm)
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{
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__tsb_context_switch(__pa(mm->pgd), mm->context.tsb_reg_val,
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mm->context.tsb_map_vaddr,
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mm->context.tsb_map_pte,
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__pa(&mm->context.tsb_descr));
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}
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extern void tsb_grow(struct mm_struct *mm, unsigned long mm_rss, gfp_t gfp_flags);
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#ifdef CONFIG_SMP
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extern void smp_tsb_sync(struct mm_struct *mm);
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#else
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#define smp_tsb_sync(__mm) do { } while (0)
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#endif
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/* Set MMU context in the actual hardware. */
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#define load_secondary_context(__mm) \
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__asm__ __volatile__( \
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"\n661: stxa %0, [%1] %2\n" \
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" .section .sun4v_1insn_patch, \"ax\"\n" \
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" .word 661b\n" \
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" stxa %0, [%1] %3\n" \
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" .previous\n" \
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" flush %%g6\n" \
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: /* No outputs */ \
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: "r" (CTX_HWBITS((__mm)->context)), \
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"r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
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extern void __flush_tlb_mm(unsigned long, unsigned long);
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/* Switch the current MM context. Interrupts are disabled. */
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static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
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{
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unsigned long ctx_valid;
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int cpu;
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spin_lock(&mm->context.lock);
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ctx_valid = CTX_VALID(mm->context);
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if (!ctx_valid)
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get_new_mmu_context(mm);
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spin_unlock(&mm->context.lock);
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if (!ctx_valid || (old_mm != mm)) {
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load_secondary_context(mm);
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tsb_context_switch(mm);
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}
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/* Even if (mm == old_mm) we _must_ check
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* the cpu_vm_mask. If we do not we could
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* corrupt the TLB state because of how
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* smp_flush_tlb_{page,range,mm} on sparc64
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* and lazy tlb switches work. -DaveM
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*/
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cpu = smp_processor_id();
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if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
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cpu_set(cpu, mm->cpu_vm_mask);
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__flush_tlb_mm(CTX_HWBITS(mm->context),
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SECONDARY_CONTEXT);
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}
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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/* Activate a new MM instance for the current task. */
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static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
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{
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unsigned long flags;
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int cpu;
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spin_lock_irqsave(&mm->context.lock, flags);
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if (!CTX_VALID(mm->context))
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get_new_mmu_context(mm);
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cpu = smp_processor_id();
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if (!cpu_isset(cpu, mm->cpu_vm_mask))
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cpu_set(cpu, mm->cpu_vm_mask);
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spin_unlock_irqrestore(&mm->context.lock, flags);
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load_secondary_context(mm);
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__flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
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tsb_context_switch(mm);
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__SPARC64_MMU_CONTEXT_H) */
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