a5c474580b
Most of the AT91RM9200 user peripherals are also integrated into the Atmel SAM9 range of processors. This patch renames the headers from at91rm9200_xx.h to at91_xx.h to indicate they're not at91rm9200-specific. The new SAM9-specific registers and register bits have also been defined. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
57 lines
2.3 KiB
C
57 lines
2.3 KiB
C
/*
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* include/asm-arm/arch-at91rm9200/at91_twi.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Two-wire Interface (TWI) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_TWI_H
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#define AT91_TWI_H
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#define AT91_TWI_CR 0x00 /* Control Register */
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#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
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#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
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#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
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#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
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#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
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#define AT91_TWI_MMR 0x04 /* Master Mode Register */
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#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
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#define AT91_TWI_IADRSZ_NO (0 << 8)
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#define AT91_TWI_IADRSZ_1 (1 << 8)
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#define AT91_TWI_IADRSZ_2 (2 << 8)
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#define AT91_TWI_IADRSZ_3 (3 << 8)
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#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
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#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
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#define AT91_TWI_IADR 0x0c /* Internal Address Register */
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#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
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#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
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#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
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#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
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#define AT91_TWI_SR 0x20 /* Status Register */
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#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
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#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
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#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
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#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
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#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
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#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
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#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
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#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
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#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
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#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
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#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
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#endif
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