5470dc6568
In the old days when arm26/arm32 was combined into the same architecture, proc-fns.h provided the xchg implementation for arm26 CPUs. Since we no longer combine these two, this include is no longer required. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
414 lines
10 KiB
C
414 lines
10 KiB
C
#ifndef __ASM_ARM_SYSTEM_H
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#define __ASM_ARM_SYSTEM_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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#define CPU_ARCH_UNKNOWN 0
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#define CPU_ARCH_ARMv3 1
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#define CPU_ARCH_ARMv4 2
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#define CPU_ARCH_ARMv4T 3
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#define CPU_ARCH_ARMv5 4
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#define CPU_ARCH_ARMv5T 5
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#define CPU_ARCH_ARMv5TE 6
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#define CPU_ARCH_ARMv5TEJ 7
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#define CPU_ARCH_ARMv6 8
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CPUID_ID 0
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#define CPUID_CACHETYPE 1
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#define CPUID_TCM 2
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#define CPUID_TLBTYPE 3
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#define read_cpuid(reg) \
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({ \
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unsigned int __val; \
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asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
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: "=r" (__val) \
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: \
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: "cc"); \
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__val; \
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})
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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* the compiler from one version to another so a bit of paranoia won't hurt.
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* This string is meant to be concatenated with the inline asm string and
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* will cause compilation to stop on mismatch.
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* (for details, see gcc PR 15089)
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*/
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#ifndef __ASSEMBLY__
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#include <linux/linkage.h>
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struct thread_info;
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struct task_struct;
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/* information about the system we're running on */
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extern unsigned int system_rev;
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extern unsigned int system_serial_low;
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extern unsigned int system_serial_high;
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extern unsigned int mem_fclk_21285;
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struct pt_regs;
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void die(const char *msg, struct pt_regs *regs, int err)
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__attribute__((noreturn));
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struct siginfo;
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void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
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unsigned long err, unsigned long trap);
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void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
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struct pt_regs *),
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int sig, const char *name);
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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extern asmlinkage void __backtrace(void);
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extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
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struct mm_struct;
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extern void show_pte(struct mm_struct *mm, unsigned long addr);
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extern void __show_regs(struct pt_regs *);
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extern int cpu_architecture(void);
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extern void cpu_init(void);
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#define set_cr(x) \
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__asm__ __volatile__( \
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"mcr p15, 0, %0, c1, c0, 0 @ set CR" \
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: : "r" (x) : "cc")
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#define get_cr() \
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({ \
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unsigned int __val; \
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__asm__ __volatile__( \
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"mrc p15, 0, %0, c1, c0, 0 @ get CR" \
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: "=r" (__val) : : "cc"); \
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__val; \
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})
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extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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#define UDBG_UNDEFINED (1 << 0)
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#define UDBG_SYSCALL (1 << 1)
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#define UDBG_BADABORT (1 << 2)
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#define UDBG_SEGV (1 << 3)
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#define UDBG_BUS (1 << 4)
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extern unsigned int user_debug;
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#if __LINUX_ARM_ARCH__ >= 4
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#define vectors_high() (cr_alignment & CR_V)
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#else
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#define vectors_high() (0)
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#endif
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#if __LINUX_ARM_ARCH__ >= 6
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#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#else
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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#endif
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#define rmb() mb()
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#define wmb() mb()
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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/*
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* switch_mm() may do a full cache flush over the context switch,
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* so enable interrupts over the context switch to avoid high
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* latency.
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*/
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#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'. schedule() itself
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* contains the memory barrier to tell GCC not to cache `current'.
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*/
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extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
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#define switch_to(prev,next,last) \
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do { \
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last = __switch_to(prev,prev->thread_info,next->thread_info); \
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} while (0)
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/*
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* CPU interrupt mask handling.
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*/
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#if __LINUX_ARM_ARCH__ >= 6
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#define local_irq_save(x) \
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({ \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_save\n" \
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"cpsid i" \
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: "=r" (x) : : "memory", "cc"); \
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})
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#define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
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#define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
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#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
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#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
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#else
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/*
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* Save the current interrupt enable state & disable IRQs
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*/
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#define local_irq_save(x) \
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({ \
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unsigned long temp; \
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(void) (&temp == &x); \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_save\n" \
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" orr %1, %0, #128\n" \
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" msr cpsr_c, %1" \
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: "=r" (x), "=r" (temp) \
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: \
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: "memory", "cc"); \
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})
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/*
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* Enable IRQs
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*/
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#define local_irq_enable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_enable\n" \
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" bic %0, %0, #128\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory", "cc"); \
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})
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/*
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* Disable IRQs
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*/
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#define local_irq_disable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_disable\n" \
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" orr %0, %0, #128\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory", "cc"); \
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})
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/*
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* Enable FIQs
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*/
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#define local_fiq_enable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ stf\n" \
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" bic %0, %0, #64\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory", "cc"); \
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})
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/*
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* Disable FIQs
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*/
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#define local_fiq_disable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ clf\n" \
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" orr %0, %0, #64\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory", "cc"); \
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})
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#endif
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/*
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* Save the current interrupt enable state.
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*/
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#define local_save_flags(x) \
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({ \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_save_flags" \
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: "=r" (x) : : "memory", "cc"); \
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})
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/*
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* restore saved IRQ & FIQ state
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*/
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#define local_irq_restore(x) \
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__asm__ __volatile__( \
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"msr cpsr_c, %0 @ local_irq_restore\n" \
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: \
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: "r" (x) \
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: "memory", "cc")
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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(int)(flags & PSR_I_BIT); \
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})
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif /* CONFIG_SMP */
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#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
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/*
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* On the StrongARM, "swp" is terminally broken since it bypasses the
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* cache totally. This means that the cache becomes inconsistent, and,
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* since we use normal loads/stores as well, this is really bad.
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* Typically, this causes oopsen in filp_close, but could have other,
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* more disasterous effects. There are two work-arounds:
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* 1. Disable interrupts and emulate the atomic swap
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* 2. Clean the cache, perform atomic swap, flush the cache
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*
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* We choose (1) since its the "easiest" to achieve here and is not
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* dependent on the processor type.
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*
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* NOTE that this solution won't work on an SMP system, so explcitly
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* forbid it here.
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*/
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#define swp_is_buggy
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#endif
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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{
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extern void __bad_xchg(volatile void *, int);
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unsigned long ret;
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#ifdef swp_is_buggy
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unsigned long flags;
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#endif
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#if __LINUX_ARM_ARCH__ >= 6
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unsigned int tmp;
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#endif
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switch (size) {
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#if __LINUX_ARM_ARCH__ >= 6
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case 1:
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asm volatile("@ __xchg1\n"
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"1: ldrexb %0, [%3]\n"
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" strexb %1, %2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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case 4:
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asm volatile("@ __xchg4\n"
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"1: ldrex %0, [%3]\n"
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" strex %1, %2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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#elif defined(swp_is_buggy)
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#ifdef CONFIG_SMP
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#error SMP is not supported on this platform
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#endif
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case 1:
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local_irq_save(flags);
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ret = *(volatile unsigned char *)ptr;
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*(volatile unsigned char *)ptr = x;
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local_irq_restore(flags);
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break;
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case 4:
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local_irq_save(flags);
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ret = *(volatile unsigned long *)ptr;
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*(volatile unsigned long *)ptr = x;
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local_irq_restore(flags);
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break;
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#else
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case 1:
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asm volatile("@ __xchg1\n"
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" swpb %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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case 4:
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asm volatile("@ __xchg4\n"
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" swp %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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#endif
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default:
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__bad_xchg(ptr, size), ret = 0;
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break;
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}
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return ret;
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}
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#endif /* __ASSEMBLY__ */
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif
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