9a799d7103
This patch adds support for the Intel 82598 PCI-Express 10GbE
chipset. Devices will be available on the market soon.
This version of the driver is largely the same as the last release:
* Driver uses a single RX and single TX queue, each using 1 MSI-X
irq vector.
* Driver runs in NAPI mode only
* Driver is largely multiqueue-ready (TM)
Changes since 20070803:
* removed wrappers for hardware functions
* incorporated e1000e-style HW api reorganization code
* sparse/checkpatch cleanups, namespace cleanups
* driver prints out extra debugging information at load time
identifying adapter board number, mac, phy types
* removed ixgbe_api.c, ixgbe_api.h, ixgbe_osdep.h
* driver update to 1.1.18
* removed ixgbe.txt which contained no useful info anymore
[ Integrated napi_struct changes from Auke as well... -DaveM ]
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Ayyappan Veeraiyan <ayyappan.veeraiyan@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
494 lines
13 KiB
C
494 lines
13 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2007 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include "ixgbe_common.h"
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#include "ixgbe_phy.h"
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static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
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static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
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static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
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static s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 phy_data);
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/**
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* ixgbe_identify_phy - Get physical layer module
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* @hw: pointer to hardware structure
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*
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* Determines the physical layer module found on the current adapter.
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**/
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s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
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{
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s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
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u32 phy_addr;
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for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
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if (ixgbe_validate_phy_addr(hw, phy_addr)) {
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hw->phy.addr = phy_addr;
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ixgbe_get_phy_id(hw);
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hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
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status = 0;
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break;
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}
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}
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return status;
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}
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/**
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* ixgbe_validate_phy_addr - Determines phy address is valid
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* @hw: pointer to hardware structure
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*
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**/
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static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
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{
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u16 phy_id = 0;
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bool valid = false;
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hw->phy.addr = phy_addr;
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ixgbe_read_phy_reg(hw,
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IXGBE_MDIO_PHY_ID_HIGH,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&phy_id);
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if (phy_id != 0xFFFF && phy_id != 0x0)
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valid = true;
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return valid;
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}
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/**
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* ixgbe_get_phy_id - Get the phy type
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* @hw: pointer to hardware structure
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*
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**/
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static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
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{
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u32 status;
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u16 phy_id_high = 0;
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u16 phy_id_low = 0;
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status = ixgbe_read_phy_reg(hw,
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IXGBE_MDIO_PHY_ID_HIGH,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&phy_id_high);
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if (status == 0) {
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hw->phy.id = (u32)(phy_id_high << 16);
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status = ixgbe_read_phy_reg(hw,
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IXGBE_MDIO_PHY_ID_LOW,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&phy_id_low);
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hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
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hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
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}
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return status;
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}
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/**
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* ixgbe_get_phy_type_from_id - Get the phy type
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* @hw: pointer to hardware structure
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*
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**/
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static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
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{
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enum ixgbe_phy_type phy_type;
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switch (phy_id) {
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case TN1010_PHY_ID:
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phy_type = ixgbe_phy_tn;
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break;
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case QT2022_PHY_ID:
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phy_type = ixgbe_phy_qt;
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break;
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default:
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phy_type = ixgbe_phy_unknown;
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break;
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}
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return phy_type;
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}
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/**
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* ixgbe_reset_phy - Performs a PHY reset
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* @hw: pointer to hardware structure
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**/
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s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
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{
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/*
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* Perform soft PHY reset to the PHY_XS.
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* This will cause a soft reset to the PHY
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*/
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return ixgbe_write_phy_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
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IXGBE_MDIO_PHY_XS_DEV_TYPE,
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IXGBE_MDIO_PHY_XS_RESET);
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}
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/**
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* ixgbe_read_phy_reg - Reads a value from a specified PHY register
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* @hw: pointer to hardware structure
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* @reg_addr: 32 bit address of PHY register to read
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* @phy_data: Pointer to read data from PHY register
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**/
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s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 *phy_data)
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{
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u32 command;
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u32 i;
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u32 timeout = 10;
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u32 data;
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s32 status = 0;
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u16 gssr;
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if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
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gssr = IXGBE_GSSR_PHY1_SM;
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else
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gssr = IXGBE_GSSR_PHY0_SM;
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if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
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status = IXGBE_ERR_SWFW_SYNC;
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if (status == 0) {
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/* Setup and write the address cycle command */
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle completed.
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* The MDI Command bit will clear when the operation is
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* complete
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*/
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for (i = 0; i < timeout; i++) {
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udelay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
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break;
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
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hw_dbg(hw, "PHY address command did not complete.\n");
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status = IXGBE_ERR_PHY;
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}
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if (status == 0) {
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/*
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* Address cycle complete, setup and write the read
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* command
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*/
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle
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* completed. The MDI Command bit will clear when the
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* operation is complete
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*/
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for (i = 0; i < timeout; i++) {
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udelay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
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break;
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
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hw_dbg(hw,
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"PHY read command didn't complete\n");
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status = IXGBE_ERR_PHY;
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} else {
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/*
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* Read operation is complete. Get the data
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* from MSRWD
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*/
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data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
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data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
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*phy_data = (u16)(data);
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}
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}
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ixgbe_release_swfw_sync(hw, gssr);
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}
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return status;
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}
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/**
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* ixgbe_write_phy_reg - Writes a value to specified PHY register
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* @hw: pointer to hardware structure
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* @reg_addr: 32 bit PHY register to write
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* @device_type: 5 bit device type
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* @phy_data: Data to write to the PHY register
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**/
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static s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 phy_data)
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{
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u32 command;
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u32 i;
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u32 timeout = 10;
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s32 status = 0;
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u16 gssr;
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if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
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gssr = IXGBE_GSSR_PHY1_SM;
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else
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gssr = IXGBE_GSSR_PHY0_SM;
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if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
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status = IXGBE_ERR_SWFW_SYNC;
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if (status == 0) {
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/* Put the data in the MDI single read and write data register*/
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IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
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/* Setup and write the address cycle command */
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle completed.
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* The MDI Command bit will clear when the operation is
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* complete
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*/
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for (i = 0; i < timeout; i++) {
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udelay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
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hw_dbg(hw, "PHY address cmd didn't complete\n");
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break;
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}
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0)
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status = IXGBE_ERR_PHY;
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if (status == 0) {
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/*
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* Address cycle complete, setup and write the write
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* command
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*/
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command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
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(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
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(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
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(IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
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IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
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/*
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* Check every 10 usec to see if the address cycle
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* completed. The MDI Command bit will clear when the
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* operation is complete
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*/
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for (i = 0; i < timeout; i++) {
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udelay(10);
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command = IXGBE_READ_REG(hw, IXGBE_MSCA);
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if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
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hw_dbg(hw, "PHY write command did not "
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"complete.\n");
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break;
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}
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}
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if ((command & IXGBE_MSCA_MDI_COMMAND) != 0)
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status = IXGBE_ERR_PHY;
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}
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ixgbe_release_swfw_sync(hw, gssr);
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}
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return status;
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}
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/**
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* ixgbe_setup_tnx_phy_link - Set and restart autoneg
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* @hw: pointer to hardware structure
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*
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* Restart autonegotiation and PHY and waits for completion.
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**/
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s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw)
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{
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s32 status = IXGBE_NOT_IMPLEMENTED;
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u32 time_out;
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u32 max_time_out = 10;
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u16 autoneg_speed_selection_register = 0x10;
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u16 autoneg_restart_mask = 0x0200;
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u16 autoneg_complete_mask = 0x0020;
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u16 autoneg_reg = 0;
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/*
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* Set advertisement settings in PHY based on autoneg_advertised
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* settings. If autoneg_advertised = 0, then advertise default values
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* txn devices cannot be "forced" to a autoneg 10G and fail. But can
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* for a 1G.
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*/
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ixgbe_read_phy_reg(hw,
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autoneg_speed_selection_register,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_reg);
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if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
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autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
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else
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autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
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ixgbe_write_phy_reg(hw,
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autoneg_speed_selection_register,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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autoneg_reg);
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/* Restart PHY autonegotiation and wait for completion */
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ixgbe_read_phy_reg(hw,
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IXGBE_MDIO_AUTO_NEG_CONTROL,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_reg);
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autoneg_reg |= autoneg_restart_mask;
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ixgbe_write_phy_reg(hw,
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IXGBE_MDIO_AUTO_NEG_CONTROL,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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autoneg_reg);
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/* Wait for autonegotiation to finish */
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for (time_out = 0; time_out < max_time_out; time_out++) {
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udelay(10);
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/* Restart PHY autonegotiation and wait for completion */
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status = ixgbe_read_phy_reg(hw,
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IXGBE_MDIO_AUTO_NEG_STATUS,
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IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
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&autoneg_reg);
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autoneg_reg &= autoneg_complete_mask;
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if (autoneg_reg == autoneg_complete_mask) {
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status = 0;
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break;
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}
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}
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if (time_out == max_time_out)
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status = IXGBE_ERR_LINK_SETUP;
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return status;
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}
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/**
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* ixgbe_check_tnx_phy_link - Determine link and speed status
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* @hw: pointer to hardware structure
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*
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* Reads the VS1 register to determine if link is up and the current speed for
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* the PHY.
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**/
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s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw, u32 *speed,
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bool *link_up)
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{
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s32 status = 0;
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u32 time_out;
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u32 max_time_out = 10;
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u16 phy_link = 0;
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u16 phy_speed = 0;
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u16 phy_data = 0;
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/* Initialize speed and link to default case */
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*link_up = false;
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*speed = IXGBE_LINK_SPEED_10GB_FULL;
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/*
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* Check current speed and link status of the PHY register.
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* This is a vendor specific register and may have to
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* be changed for other copper PHYs.
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*/
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for (time_out = 0; time_out < max_time_out; time_out++) {
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udelay(10);
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if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
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*link_up = true;
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if (phy_speed ==
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IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
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*speed = IXGBE_LINK_SPEED_1GB_FULL;
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break;
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} else {
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status = ixgbe_read_phy_reg(hw,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
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IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
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&phy_data);
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phy_link = phy_data &
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IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
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phy_speed = phy_data &
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IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
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}
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}
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return status;
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}
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/**
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* ixgbe_setup_tnx_phy_link_speed - Sets the auto advertised capabilities
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* @hw: pointer to hardware structure
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* @speed: new link speed
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* @autoneg: true if autonegotiation enabled
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**/
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s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw, u32 speed,
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bool autoneg,
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bool autoneg_wait_to_complete)
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{
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/*
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* Clear autoneg_advertised and set new values based on input link
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* speed.
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*/
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hw->phy.autoneg_advertised = 0;
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if (speed & IXGBE_LINK_SPEED_10GB_FULL)
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
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if (speed & IXGBE_LINK_SPEED_1GB_FULL)
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
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/* Setup link based on the new speed settings */
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ixgbe_setup_tnx_phy_link(hw);
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return 0;
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}
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