db331fc8fc
Add SCIF serial port support to the r8a7778 SoC by adding platform devices together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
193 lines
5 KiB
C
193 lines
5 KiB
C
/*
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* r8a7778 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/irqchip.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <mach/irqs.h>
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#include <mach/r8a7778.h>
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#include <mach/common.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/cache-l2x0.h>
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/* SCIF */
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#define SCIF_INFO(baseaddr, irq) \
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{ \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
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.scbrr_algo_id = SCBRR_ALGO_2, \
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.type = PORT_SCIF, \
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.irqs = SCIx_IRQ_MUXED(irq), \
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}
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static struct plat_sci_port scif_platform_data[] = {
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SCIF_INFO(0xffe40000, gic_iid(0x66)),
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SCIF_INFO(0xffe41000, gic_iid(0x67)),
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SCIF_INFO(0xffe42000, gic_iid(0x68)),
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SCIF_INFO(0xffe43000, gic_iid(0x69)),
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SCIF_INFO(0xffe44000, gic_iid(0x6a)),
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SCIF_INFO(0xffe45000, gic_iid(0x6b)),
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};
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/* TMU */
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static struct resource sh_tmu0_resources[] = {
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DEFINE_RES_MEM(0xffd80008, 12),
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DEFINE_RES_IRQ(gic_iid(0x40)),
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};
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static struct sh_timer_config sh_tmu0_platform_data = {
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.name = "TMU00",
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.channel_offset = 0x4,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource sh_tmu1_resources[] = {
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DEFINE_RES_MEM(0xffd80014, 12),
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DEFINE_RES_IRQ(gic_iid(0x41)),
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};
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static struct sh_timer_config sh_tmu1_platform_data = {
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.name = "TMU01",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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#define PLATFORM_INFO(n, i) \
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{ \
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.parent = &platform_bus, \
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.name = #n, \
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.id = i, \
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.res = n ## i ## _resources, \
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.num_res = ARRAY_SIZE(n ## i ##_resources), \
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.data = &n ## i ##_platform_data, \
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.size_data = sizeof(n ## i ## _platform_data), \
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}
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struct platform_device_info platform_devinfo[] = {
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PLATFORM_INFO(sh_tmu, 0),
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PLATFORM_INFO(sh_tmu, 1),
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};
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void __init r8a7778_add_standard_devices(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
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if (base) {
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/*
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* Early BRESP enable, Shared attribute override enable, 64K*16way
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* don't call iounmap(base)
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*/
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l2x0_init(base, 0x40470000, 0x82000fff);
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}
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#endif
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for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
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platform_device_register_data(&platform_bus, "sh-sci", i,
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&scif_platform_data[i],
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sizeof(struct plat_sci_port));
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for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
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platform_device_register_full(&platform_devinfo[i]);
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}
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#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
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#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
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#define INT2NTSR0 0x00018 /* 0xfe700018 */
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#define INT2NTSR1 0x0002c /* 0xfe70002c */
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static void __init r8a7778_init_irq_common(void)
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{
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void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
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BUG_ON(!base);
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/* route all interrupts to ARM */
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__raw_writel(0x73ffffff, base + INT2NTSR0);
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__raw_writel(0xffffffff, base + INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0x08330773, base + INT2SMSKCR0);
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__raw_writel(0x00311110, base + INT2SMSKCR1);
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iounmap(base);
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}
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void __init r8a7778_init_irq(void)
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{
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void __iomem *gic_dist_base;
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void __iomem *gic_cpu_base;
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gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
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gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
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BUG_ON(!gic_dist_base || !gic_cpu_base);
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/* use GIC to handle interrupts */
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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r8a7778_init_irq_common();
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}
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void __init r8a7778_init_delay(void)
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{
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shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
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}
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#ifdef CONFIG_USE_OF
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void __init r8a7778_init_irq_dt(void)
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{
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irqchip_init();
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r8a7778_init_irq_common();
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}
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static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
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{},
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};
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void __init r8a7778_add_standard_devices_dt(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table,
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r8a7778_auxdata_lookup, NULL);
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}
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static const char *r8a7778_compat_dt[] __initdata = {
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"renesas,r8a7778",
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NULL,
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};
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DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
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.init_early = r8a7778_init_delay,
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.init_irq = r8a7778_init_irq_dt,
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.init_machine = r8a7778_add_standard_devices_dt,
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.init_time = shmobile_timer_init,
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.dt_compat = r8a7778_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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