23db472bba
This adds helper functions to calculate parameters required for base module format and copier module. A generic module is modelled by base module. Copier module is responsible for getting/sending data to FE (host DMAs) and BE (link HDA DMA, SSP, PDM) This also ads module pin management helpers which help in finding pins to use or freeing them up Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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* skl-tplg-interface.h - Intel DSP FW private data interface
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*
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* Copyright (C) 2015 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* Nilofer, Samreen <samreen.nilofer@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __HDA_TPLG_INTERFACE_H__
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#define __HDA_TPLG_INTERFACE_H__
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/**
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* enum skl_ch_cfg - channel configuration
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*
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* @SKL_CH_CFG_MONO: One channel only
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* @SKL_CH_CFG_STEREO: L & R
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* @SKL_CH_CFG_2_1: L, R & LFE
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* @SKL_CH_CFG_3_0: L, C & R
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* @SKL_CH_CFG_3_1: L, C, R & LFE
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* @SKL_CH_CFG_QUATRO: L, R, Ls & Rs
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* @SKL_CH_CFG_4_0: L, C, R & Cs
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* @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
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* @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
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* @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
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* @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
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* @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
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* @SKL_CH_CFG_INVALID: Invalid
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*/
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enum skl_ch_cfg {
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SKL_CH_CFG_MONO = 0,
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SKL_CH_CFG_STEREO = 1,
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SKL_CH_CFG_2_1 = 2,
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SKL_CH_CFG_3_0 = 3,
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SKL_CH_CFG_3_1 = 4,
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SKL_CH_CFG_QUATRO = 5,
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SKL_CH_CFG_4_0 = 6,
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SKL_CH_CFG_5_0 = 7,
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SKL_CH_CFG_5_1 = 8,
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SKL_CH_CFG_DUAL_MONO = 9,
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SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
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SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
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SKL_CH_CFG_INVALID
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};
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enum skl_module_type {
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SKL_MODULE_TYPE_MIXER = 0,
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SKL_MODULE_TYPE_COPIER,
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SKL_MODULE_TYPE_UPDWMIX,
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SKL_MODULE_TYPE_SRCINT
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};
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enum skl_core_affinity {
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SKL_AFFINITY_CORE_0 = 0,
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SKL_AFFINITY_CORE_1,
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SKL_AFFINITY_CORE_MAX
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};
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enum skl_pipe_conn_type {
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SKL_PIPE_CONN_TYPE_NONE = 0,
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SKL_PIPE_CONN_TYPE_FE,
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SKL_PIPE_CONN_TYPE_BE
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};
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enum skl_hw_conn_type {
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SKL_CONN_NONE = 0,
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SKL_CONN_SOURCE = 1,
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SKL_CONN_SINK = 2
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};
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enum skl_dev_type {
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SKL_DEVICE_BT = 0x0,
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SKL_DEVICE_DMIC = 0x1,
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SKL_DEVICE_I2S = 0x2,
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SKL_DEVICE_SLIMBUS = 0x3,
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SKL_DEVICE_HDALINK = 0x4,
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SKL_DEVICE_NONE
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};
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#endif
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