b1526421ea
cx18: Create cx18_ specific wrappers for all pci mmio accessesors. This is a first step in instrumenting all CX23418 PCI bus IO, to debug problems with accessing the CX23418's PCI memory mapped IO. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
/*
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* cx18 driver PCI memory mapped IO access routines
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#include "cx18-driver.h"
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#include "cx18-irq.h"
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void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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__raw_writel(val, addr);
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}
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u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
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{
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return __raw_readl(addr);
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}
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u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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writel(val, addr);
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return readl(addr);
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}
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void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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writel(val, addr);
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}
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u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
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{
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return readl(addr);
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}
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/* Access "register" region of CX23418 memory mapped I/O */
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u32 cx18_read_reg(struct cx18 *cx, u32 reg)
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{
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return readl(cx->reg_mem + reg);
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}
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void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
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{
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writel(val, cx->reg_mem + reg);
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}
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u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg)
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{
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return cx18_write_sync(cx, val, cx->reg_mem + reg);
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}
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/* Access "encoder memory" region of CX23418 memory mapped I/O */
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u32 cx18_read_enc(struct cx18 *cx, u32 addr)
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{
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return readl(cx->enc_mem + addr);
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}
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void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
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{
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writel(val, cx->enc_mem + addr);
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}
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u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
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{
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return cx18_write_sync(cx, val, cx->enc_mem + addr);
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}
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void cx18_memcpy_fromio(struct cx18 *cx, void *to,
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const void __iomem *from, unsigned int len)
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{
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memcpy_fromio(to, from, len);
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}
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void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
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{
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memset_io(addr, val, count);
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}
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void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
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{
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u32 r;
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cx18_write_reg(cx, val, SW1_INT_STATUS);
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r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
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cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
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}
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void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
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{
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u32 r;
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r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
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cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
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{
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u32 r;
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cx18_write_reg(cx, val, SW2_INT_STATUS);
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r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
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cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
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{
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u32 r;
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r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
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cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI);
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}
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void cx18_setup_page(struct cx18 *cx, u32 addr)
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{
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u32 val;
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val = cx18_read_reg(cx, 0xD000F8);
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val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
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cx18_write_reg(cx, val, 0xD000F8);
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}
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/* Tries to recover from the CX23418 responding improperly on the PCI bus */
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int cx18_pci_try_recover(struct cx18 *cx)
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{
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u16 status;
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pci_read_config_word(cx->dev, PCI_STATUS, &status);
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pci_write_config_word(cx->dev, PCI_STATUS, status);
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return 0;
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}
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