390167efa3
Currently there are several dts that don't specify address or size cells for the muram. This causes dtc to use default values, one of which is an address-cells of two, and this breaks the parsing of the muram ranges, which is assuming an address-cells of one. For example: Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Explicitly setting the address and size cells gets it parsed properly and gets rid of the four dtc warnings. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
473 lines
10 KiB
Text
473 lines
10 KiB
Text
/*
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* MPC8568E MDS Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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/memreserve/ 00000000 1000000;
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*/
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/ {
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model = "MPC8568EMDS";
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compatible = "MPC8568EMDS", "MPC85xxMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8568@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 10000000>;
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};
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bcsr@f8000000 {
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device_type = "board-control";
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reg = <f8000000 8000>;
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};
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soc8568@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00001000>;
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8568-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <12 2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8568-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <10 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <68>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <3100 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <24520 20>;
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phy0: ethernet-phy@7 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <7>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1d 2 1e 2 22 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <25000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <23 2 24 2 28 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy3>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,mpc8548-guts";
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reg = <e0000 1000>;
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fsl,has-rstcr;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 f000>;
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interrupts = <2d 2>;
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interrupt-parent = <&mpic>;
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num-channels = <4>;
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channel-fifo-len = <18>;
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exec-units-mask = <000000fe>;
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descriptor-types-mask = <012b0ebf>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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par_io@e0100 {
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reg = <e0100 100>;
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device_type = "par_io";
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num-ports = <7>;
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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4 0a 1 0 2 0 /* TxD0 */
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4 09 1 0 2 0 /* TxD1 */
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4 08 1 0 2 0 /* TxD2 */
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4 07 1 0 2 0 /* TxD3 */
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4 17 1 0 2 0 /* TxD4 */
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4 16 1 0 2 0 /* TxD5 */
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4 15 1 0 2 0 /* TxD6 */
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4 14 1 0 2 0 /* TxD7 */
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4 0f 2 0 2 0 /* RxD0 */
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4 0e 2 0 2 0 /* RxD1 */
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4 0d 2 0 2 0 /* RxD2 */
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4 0c 2 0 2 0 /* RxD3 */
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4 1d 2 0 2 0 /* RxD4 */
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4 1c 2 0 2 0 /* RxD5 */
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4 1b 2 0 2 0 /* RxD6 */
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4 1a 2 0 2 0 /* RxD7 */
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4 0b 1 0 2 0 /* TX_EN */
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4 18 1 0 2 0 /* TX_ER */
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4 10 2 0 2 0 /* RX_DV */
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4 1e 2 0 2 0 /* RX_ER */
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4 11 2 0 2 0 /* RX_CLK */
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4 13 1 0 2 0 /* GTX_CLK */
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1 1f 2 0 3 0>; /* GTX125 */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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5 0a 1 0 2 0 /* TxD0 */
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5 09 1 0 2 0 /* TxD1 */
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5 08 1 0 2 0 /* TxD2 */
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5 07 1 0 2 0 /* TxD3 */
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5 17 1 0 2 0 /* TxD4 */
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5 16 1 0 2 0 /* TxD5 */
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5 15 1 0 2 0 /* TxD6 */
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5 14 1 0 2 0 /* TxD7 */
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5 0f 2 0 2 0 /* RxD0 */
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5 0e 2 0 2 0 /* RxD1 */
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5 0d 2 0 2 0 /* RxD2 */
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5 0c 2 0 2 0 /* RxD3 */
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5 1d 2 0 2 0 /* RxD4 */
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5 1c 2 0 2 0 /* RxD5 */
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5 1b 2 0 2 0 /* RxD6 */
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5 1a 2 0 2 0 /* RxD7 */
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5 0b 1 0 2 0 /* TX_EN */
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5 18 1 0 2 0 /* TX_ER */
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5 10 2 0 2 0 /* RX_DV */
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5 1e 2 0 2 0 /* RX_ER */
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5 11 2 0 2 0 /* RX_CLK */
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5 13 1 0 2 0 /* GTX_CLK */
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1 1f 2 0 3 0 /* GTX125 */
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4 06 3 0 2 0 /* MDIO */
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4 05 1 0 2 0>; /* MDC */
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};
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};
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};
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qe@e0080000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0 e0080000 00040000>;
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reg = <e0080000 480>;
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brg-frequency = <0>;
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bus-frequency = <179A7B00>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 0000c000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 c000>;
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};
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};
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spi@4c0 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <4c0 40>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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spi@500 {
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cell-index = <1>;
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compatible = "fsl,spi";
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reg = <500 40>;
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interrupts = <1>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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enet2: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <1>;
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device-id = <1>;
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reg = <2000 200>;
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interrupts = <20>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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pio-handle = <&pio1>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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enet3: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <2>;
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device-id = <2>;
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reg = <3000 200>;
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interrupts = <21>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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pio-handle = <&pio2>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@2120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2120 18>;
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compatible = "fsl,ucc-mdio";
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/* These are the same PHYs as on
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* gianfar's MDIO bus */
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qe_phy0: ethernet-phy@07 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <7>;
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device_type = "ethernet-phy";
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};
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qe_phy1: ethernet-phy@01 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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qe_phy2: ethernet-phy@02 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <2>;
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device_type = "ethernet-phy";
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};
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qe_phy3: ethernet-phy@03 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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big-endian;
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interrupts = <2e 2 2e 2>; //high:30 low:30
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interrupt-parent = <&mpic>;
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};
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};
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pci0: pci@e0008000 {
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cell-index = <0>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x12 AD18 */
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9000 0 0 1 &mpic 5 1
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9000 0 0 2 &mpic 6 1
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9000 0 0 3 &mpic 7 1
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9000 0 0 4 &mpic 4 1
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/* IDSEL 0x13 AD19 */
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9800 0 0 1 &mpic 6 1
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9800 0 0 2 &mpic 7 1
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9800 0 0 3 &mpic 4 1
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9800 0 0 4 &mpic 5 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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bus-range = <0 ff>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 00800000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008000 1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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};
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/* PCI Express */
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pci1: pcie@e000a000 {
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cell-index = <2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 (PEX) */
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00000 0 0 1 &mpic 0 1
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00000 0 0 2 &mpic 1 1
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00000 0 0 3 &mpic 2 1
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00000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <1a 2>;
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bus-range = <0 ff>;
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ranges = <02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 e2800000 0 00800000>;
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clock-frequency = <1fca055>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e000a000 1000>;
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 a0000000
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02000000 0 a0000000
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0 10000000
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01000000 0 00000000
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01000000 0 00000000
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0 00800000>;
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};
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};
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};
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