18dabf473e
Change the page member of the scatterlist structure to be an unsigned long, and encode more stuff in the lower bits: - Bits 0 and 1 zero: this is a normal sg entry. Next sg entry is located at sg + 1. - Bit 0 set: this is a chain entry, the next real entry is at ->page_link with the two low bits masked off. - Bit 1 set: this is the final entry in the sg entry. sg_next() will return NULL when passed such an entry. It's thus important that sg table users use the proper accessors to get and set the page member. Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
187 lines
4.3 KiB
C
187 lines
4.3 KiB
C
#ifndef _ASM_I386_DMA_MAPPING_H
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#define _ASM_I386_DMA_MAPPING_H
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#include <linux/mm.h>
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#include <linux/scatterlist.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/bug.h>
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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void dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle);
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static inline dma_addr_t
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dma_map_single(struct device *dev, void *ptr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(size == 0);
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flush_write_buffers();
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return virt_to_phys(ptr);
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}
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static inline void
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dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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}
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static inline int
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dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nents == 0 || sglist[0].length == 0);
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for_each_sg(sglist, sg, nents, i) {
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BUG_ON(!sg_page(sg));
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sg->dma_address = sg_phys(sg);
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}
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flush_write_buffers();
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return nents;
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}
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static inline dma_addr_t
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dma_map_page(struct device *dev, struct page *page, unsigned long offset,
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size_t size, enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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return page_to_phys(page) + offset;
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}
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static inline void
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dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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}
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static inline void
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dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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}
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static inline void
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dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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}
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static inline void
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dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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flush_write_buffers();
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}
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static inline void
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dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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}
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static inline void
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dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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flush_write_buffers();
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}
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static inline void
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dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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}
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static inline void
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dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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flush_write_buffers();
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}
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static inline int
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dma_mapping_error(dma_addr_t dma_addr)
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{
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return 0;
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}
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extern int forbid_dac;
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static inline int
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dma_supported(struct device *dev, u64 mask)
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{
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/*
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* we fall back to GFP_DMA when the mask isn't all 1s,
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* so we can't guarantee allocations that must be
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* within a tighter range than GFP_DMA..
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*/
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if(mask < 0x00ffffff)
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return 0;
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/* Work around chipset bugs */
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if (forbid_dac > 0 && mask > 0xffffffffULL)
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return 0;
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return 1;
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}
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static inline int
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dma_set_mask(struct device *dev, u64 mask)
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{
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if(!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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static inline int
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dma_get_cache_alignment(void)
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{
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/* no easy way to get cache size on all x86, so return the
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* maximum possible, to be safe */
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return (1 << INTERNODE_CACHE_SHIFT);
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}
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#define dma_is_consistent(d, h) (1)
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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flush_write_buffers();
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}
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#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
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extern int
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dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
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dma_addr_t device_addr, size_t size, int flags);
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extern void
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dma_release_declared_memory(struct device *dev);
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extern void *
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dma_mark_declared_memory_occupied(struct device *dev,
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dma_addr_t device_addr, size_t size);
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#endif
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