22258fa40e
This patch extends the Ebony and Walnut platform code to instantiate the existing ds1742 RTC class driver for the DS1743 RTC/NVRAM chip found on both those boards. The patch uses a helper function to scan the device tree and instantiate the appropriate platform_device based on it, so it should be easy to extend for other boards which have mmio mapped RTC chips. Along with this, the device tree binding for the ds1743 chips is tweaked, based on the existing DS1385 OF binding found at: http://playground.sun.com/1275/proposals/Closed/Remanded/Accepted/346-it.txt Although that document covers the NVRAM portion of the chip, whereas here we're interested in the RTC portion, so it's not entirely clear if that's a good model. This implements only RTC class driver support - that is /dev/rtc0, not /dev/rtc, and the low-level get/set time callbacks remain unimplemented. That means in order to get at the clock you will either need a modified version of hwclock which will look at /dev/rtc0, or you'll need to configure udev to symlink rtc0 to rtc. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
339 lines
7.6 KiB
Text
339 lines
7.6 KiB
Text
/*
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* Device Tree Source for IBM Ebony
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*
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* Copyright (c) 2006, 2007 IBM Corp.
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* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
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*
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* FIXME: Draft only!
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "ibm,ebony";
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compatible = "ibm,ebony";
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dcr-parent = <&/cpus/cpu@0>;
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aliases {
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ethernet0 = &EMAC0;
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ethernet1 = &EMAC1;
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,440GP";
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reg = <0>;
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clock-frequency = <0>; // Filled in by zImage
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timebase-frequency = <0>; // Filled in by zImage
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i-cache-line-size = <20>;
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d-cache-line-size = <20>;
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i-cache-size = <8000>; /* 32 kB */
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d-cache-size = <8000>; /* 32 kB */
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0 0 0>; // Filled in by zImage
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-440gp", "ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0c0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-440gp", "ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0d0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <1e 4 1f 4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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CPC0: cpc {
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compatible = "ibm,cpc-440gp";
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dcr-reg = <0b0 003 0e0 010>;
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// FIXME: anything else?
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};
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plb {
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compatible = "ibm,plb-440gp", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; // Filled in by zImage
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SDRAM0: memory-controller {
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compatible = "ibm,sdram-440gp";
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dcr-reg = <010 2>;
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// FIXME: anything else?
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};
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SRAM0: sram {
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compatible = "ibm,sram-440gp";
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dcr-reg = <020 8 00a 1>;
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};
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DMA0: dma {
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// FIXME: ???
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compatible = "ibm,dma-440gp";
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dcr-reg = <100 027>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-440gp", "ibm,mcmal";
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dcr-reg = <180 62>;
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num-tx-chans = <4>;
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num-rx-chans = <4>;
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interrupt-parent = <&MAL0>;
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interrupts = <0 1 2 3 4>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
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/*RXEOB*/ 1 &UIC0 b 4
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/*SERR*/ 2 &UIC1 0 4
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/*TXDE*/ 3 &UIC1 1 4
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/*RXDE*/ 4 &UIC1 2 4>;
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interrupt-map-mask = <ffffffff>;
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};
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POB0: opb {
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compatible = "ibm,opb-440gp", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Wish there was a nicer way of specifying a full 32-bit
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range */
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ranges = <00000000 1 00000000 80000000
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80000000 1 80000000 80000000>;
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dcr-reg = <090 00b>;
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interrupt-parent = <&UIC1>;
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interrupts = <7 4>;
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clock-frequency = <0>; // Filled in by zImage
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EBC0: ebc {
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compatible = "ibm,ebc-440gp", "ibm,ebc";
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dcr-reg = <012 2>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; // Filled in by zImage
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// ranges property is supplied by zImage
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// based on firmware's configuration of the
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// EBC bridge
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interrupts = <5 4>;
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interrupt-parent = <&UIC1>;
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small-flash@0,80000 {
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compatible = "jedec-flash";
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bank-width = <1>;
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reg = <0 80000 80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "OpenBIOS";
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reg = <0 80000>;
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read-only;
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};
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};
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nvram@1,0 {
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/* NVRAM & RTC */
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compatible = "ds1743-nvram";
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#bytes = <2000>;
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reg = <1 0 2000>;
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};
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large-flash@2,0 {
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compatible = "jedec-flash";
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bank-width = <1>;
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reg = <2 0 400000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "fs";
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reg = <0 380000>;
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};
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partition@380000 {
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label = "firmware";
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reg = <380000 80000>;
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};
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};
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ir@3,0 {
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reg = <3 0 10>;
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};
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fpga@7,0 {
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compatible = "Ebony-FPGA";
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reg = <7 0 10>;
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virtual-reg = <e8300000>;
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};
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};
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UART0: serial@40000200 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <40000200 8>;
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virtual-reg = <e0000200>;
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clock-frequency = <A8C000>;
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current-speed = <2580>;
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interrupt-parent = <&UIC0>;
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interrupts = <0 4>;
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};
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UART1: serial@40000300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <40000300 8>;
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virtual-reg = <e0000300>;
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clock-frequency = <A8C000>;
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current-speed = <2580>;
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interrupt-parent = <&UIC0>;
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interrupts = <1 4>;
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};
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IIC0: i2c@40000400 {
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/* FIXME */
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device_type = "i2c";
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compatible = "ibm,iic-440gp", "ibm,iic";
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reg = <40000400 14>;
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interrupt-parent = <&UIC0>;
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interrupts = <2 4>;
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};
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IIC1: i2c@40000500 {
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/* FIXME */
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device_type = "i2c";
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compatible = "ibm,iic-440gp", "ibm,iic";
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reg = <40000500 14>;
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interrupt-parent = <&UIC0>;
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interrupts = <3 4>;
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};
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GPIO0: gpio@40000700 {
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/* FIXME */
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compatible = "ibm,gpio-440gp";
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reg = <40000700 20>;
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};
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ZMII0: emac-zmii@40000780 {
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compatible = "ibm,zmii-440gp", "ibm,zmii";
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reg = <40000780 c>;
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};
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EMAC0: ethernet@40000800 {
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linux,network-index = <0>;
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device_type = "network";
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compatible = "ibm,emac-440gp", "ibm,emac";
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interrupt-parent = <&UIC1>;
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interrupts = <1c 4 1d 4>;
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reg = <40000800 70>;
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local-mac-address = [000000000000]; // Filled in by zImage
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mal-device = <&MAL0>;
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mal-tx-channel = <0 1>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <5dc>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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phy-mode = "rmii";
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phy-map = <00000001>;
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zmii-device = <&ZMII0>;
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zmii-channel = <0>;
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};
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EMAC1: ethernet@40000900 {
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linux,network-index = <1>;
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device_type = "network";
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compatible = "ibm,emac-440gp", "ibm,emac";
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interrupt-parent = <&UIC1>;
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interrupts = <1e 4 1f 4>;
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reg = <40000900 70>;
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local-mac-address = [000000000000]; // Filled in by zImage
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mal-device = <&MAL0>;
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mal-tx-channel = <2 3>;
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mal-rx-channel = <1>;
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cell-index = <1>;
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max-frame-size = <5dc>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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phy-mode = "rmii";
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phy-map = <00000001>;
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zmii-device = <&ZMII0>;
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zmii-channel = <1>;
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};
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GPT0: gpt@40000a00 {
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/* FIXME */
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reg = <40000a00 d4>;
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interrupt-parent = <&UIC0>;
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interrupts = <12 4 13 4 14 4 15 4 16 4>;
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};
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};
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PCIX0: pci@20ec00000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
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primary;
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reg = <2 0ec00000 8 /* Config space access */
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0 0 0 /* no IACK cycles */
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2 0ed00000 4 /* Special cycles */
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2 0ec80000 f0 /* Internal registers */
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2 0ec80100 fc>; /* Internal messaging registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <02000000 0 80000000 00000003 80000000 0 80000000
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01000000 0 00000000 00000002 08000000 0 00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 0 80000000>;
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/* Ebony has all 4 IRQ pins tied together per slot */
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interrupt-map-mask = <f800 0 0 0>;
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interrupt-map = <
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/* IDSEL 1 */
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0800 0 0 0 &UIC0 17 8
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/* IDSEL 2 */
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1000 0 0 0 &UIC0 18 8
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/* IDSEL 3 */
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1800 0 0 0 &UIC0 19 8
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/* IDSEL 4 */
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2000 0 0 0 &UIC0 1a 8
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>;
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};
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};
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chosen {
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linux,stdout-path = "/plb/opb/serial@40000200";
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};
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};
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