bde6f5f59c
Aviod TLB flush IPIs during C3 states by voluntary leave_mm() before entering C3. The performance impact of TLB flush on C3 should not be significant with respect to C3 wakeup latency. Also, CPUs tend to flush TLB in hardware while in C3 anyways. On a 8 logical CPU system, running make -j2, the number of tlbflush IPIs goes down from 40 per second to ~ 0. Total number of interrupts during the run of this workload was ~1200 per second, which makes it ~3% savings in wakeups. There was no measurable performance or power impact however. [ akpm@linux-foundation.org: symbol export fixes. ] Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
31 lines
507 B
C
31 lines
507 B
C
#ifndef _ASM_X86_MMU_H
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#define _ASM_X86_MMU_H
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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/*
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* The x86 doesn't have a mmu context, but
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* we put the segment information here.
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*
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* cpu_vm_mask is used to optimize ldt flushing.
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*/
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typedef struct {
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void *ldt;
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#ifdef CONFIG_X86_64
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rwlock_t ldtlock;
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#endif
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int size;
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struct mutex lock;
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void *vdso;
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} mm_context_t;
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#ifdef CONFIG_SMP
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void leave_mm(int cpu);
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#else
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static inline void leave_mm(int cpu)
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{
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}
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#endif
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#endif /* _ASM_X86_MMU_H */
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