593f4a788e
Use alternatives to select the workaround for the 11AP Pentium erratum for the affected steppings on the fly rather than build time. Remove the X86_GOOD_APIC configuration option and replace all the calls to apic_write_around() with plain apic_write(), protecting accesses to the ESR as appropriate due to the 3AP Pentium erratum. Remove apic_read_around() and all its invocations altogether as not needed. Remove apic_write_atomic() and all its implementing backends. The use of ASM_OUTPUT2() is not strictly needed for input constraints, but I have used it for readability's sake. I had the feeling no one else was brave enough to do it, so I went ahead and here it is. Verified by checking the generated assembly and tested with both a 32-bit and a 64-bit configuration, also with the 11AP "feature" forced on and verified with gdb on /proc/kcore to work as expected (as an 11AP machines are quite hard to get hands on these days). Some script complained about the use of "volatile", but apic_write() needs it for the same reason and is effectively a replacement for writel(), so I have disregarded it. I am not sure what the policy wrt defconfig files is, they are generated and there is risk of a conflict resulting from an unrelated change, so I have left changes to them out. The option will get removed from them at the next run. Some testing with machines other than mine will be needed to avoid some stupid mistake, but despite its volume, the change is not really that intrusive, so I am fairly confident that because it works for me, it will everywhere. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
141 lines
3.2 KiB
C
141 lines
3.2 KiB
C
#ifndef __ASM_MACH_APIC_H
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#define __ASM_MACH_APIC_H
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <mach_apicdef.h>
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#include <asm/smp.h>
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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static inline cpumask_t target_cpus(void)
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{
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#ifdef CONFIG_SMP
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return cpu_online_map;
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#else
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return cpumask_of_cpu(0);
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#endif
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}
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#define NO_BALANCE_IRQ (0)
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#define esr_disable (0)
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#ifdef CONFIG_X86_64
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#include <asm/genapic.h>
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#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
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#define INT_DEST_MODE (genapic->int_dest_mode)
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#define TARGET_CPUS (genapic->target_cpus())
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#define apic_id_registered (genapic->apic_id_registered)
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#define init_apic_ldr (genapic->init_apic_ldr)
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#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
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#define phys_pkg_id (genapic->phys_pkg_id)
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#define vector_allocation_domain (genapic->vector_allocation_domain)
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extern void setup_apic_routing(void);
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#else
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#define INT_DELIVERY_MODE dest_LowestPrio
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#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
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#define TARGET_CPUS (target_cpus())
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static inline void init_apic_ldr(void)
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{
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unsigned long val;
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apic_write(APIC_DFR, APIC_DFR_VALUE);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
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apic_write(APIC_LDR, val);
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}
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static inline int apic_id_registered(void)
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{
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return physid_isset(GET_APIC_ID(read_apic_id()), phys_cpu_present_map);
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}
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static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
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{
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return cpus_addr(cpumask)[0];
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}
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static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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static inline void setup_apic_routing(void)
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{
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#ifdef CONFIG_X86_IO_APIC
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"Flat", nr_ioapics);
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#endif
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}
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static inline int apicid_to_node(int logical_apicid)
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{
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#ifdef CONFIG_SMP
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return apicid_2_node[hard_smp_processor_id()];
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#else
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return 0;
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#endif
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}
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#endif
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static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return physid_isset(apicid, bitmap);
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}
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static inline unsigned long check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
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{
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return phys_map;
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}
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static inline int multi_timer_check(int apic, int irq)
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{
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return 0;
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}
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/* Mapping from cpu number to logical apicid */
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static inline int cpu_to_logical_apicid(int cpu)
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{
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return 1 << cpu;
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}
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < NR_CPUS && cpu_present(mps_cpu))
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return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
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else
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return BAD_APICID;
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}
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static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
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{
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return physid_mask_of_physid(phys_apicid);
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}
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static inline void setup_portio_remap(void)
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{
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}
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static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
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}
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static inline void enable_apic_mode(void)
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{
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}
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#endif /* CONFIG_X86_LOCAL_APIC */
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#endif /* __ASM_MACH_APIC_H */
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