37c241ed66
Some boards use UART D for the main serial console, and some use UART A. UART D's clock is listed in board-dt-tegra20.c's clock table, whereas UART A's clock is not. This causes the clock code to think UART A's clock is unsed. The common clock framework turns off unused clocks at boot time. This makes the kernel appear to hang. Add UART A's clock into the clock table to prevent this. Eventually, this requirement should be handled by the UART driver, and/or properties in a board-specific device tree file. Signed-off-by: Stephen Warren <swarren@nvidia.com>
178 lines
5.1 KiB
C
178 lines
5.1 KiB
C
/*
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* nVidia Tegra device tree board support
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*
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* Copyright (C) 2010 Secret Lab Technologies, Ltd.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pda_power.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c-tegra.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/setup.h>
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#include <mach/iomap.h>
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#include <mach/irqs.h>
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#include "board.h"
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#include "board-harmony.h"
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#include "clock.h"
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#include "devices.h"
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struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
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&tegra_ehci1_pdata),
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OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
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&tegra_ehci2_pdata),
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OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
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&tegra_ehci3_pdata),
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OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
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{}
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};
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static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
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/* name parent rate enabled */
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{ "uarta", "pll_p", 216000000, true },
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{ "uartd", "pll_p", 216000000, true },
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{ "usbd", "clk_m", 12000000, false },
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{ "usb2", "clk_m", 12000000, false },
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{ "usb3", "clk_m", 12000000, false },
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{ "pll_a", "pll_p_out1", 56448000, true },
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{ "pll_a_out0", "pll_a", 11289600, true },
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{ "cdev1", NULL, 0, true },
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{ "i2s1", "pll_a_out0", 11289600, false},
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{ "i2s2", "pll_a_out0", 11289600, false},
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{ NULL, NULL, 0, 0},
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};
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static void __init tegra_dt_init(void)
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{
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tegra_clk_init_from_table(tegra_dt_clk_init_table);
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/*
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* Finished with the static registrations now; fill in the missing
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* devices
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*/
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of_platform_populate(NULL, of_default_bus_match_table,
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tegra20_auxdata_lookup, NULL);
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}
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#ifdef CONFIG_MACH_TRIMSLICE
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static void __init trimslice_init(void)
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{
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int ret;
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ret = tegra_pcie_init(true, true);
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if (ret)
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pr_err("tegra_pci_init() failed: %d\n", ret);
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}
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#endif
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#ifdef CONFIG_MACH_HARMONY
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static void __init harmony_init(void)
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{
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int ret;
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ret = harmony_regulator_init();
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if (ret) {
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pr_err("harmony_regulator_init() failed: %d\n", ret);
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return;
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}
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ret = harmony_pcie_init();
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if (ret)
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pr_err("harmony_pcie_init() failed: %d\n", ret);
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}
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#endif
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#ifdef CONFIG_MACH_PAZ00
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static void __init paz00_init(void)
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{
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tegra_paz00_wifikill_init();
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}
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#endif
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static struct {
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char *machine;
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void (*init)(void);
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} board_init_funcs[] = {
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#ifdef CONFIG_MACH_TRIMSLICE
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{ "compulab,trimslice", trimslice_init },
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#endif
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#ifdef CONFIG_MACH_HARMONY
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{ "nvidia,harmony", harmony_init },
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#endif
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#ifdef CONFIG_MACH_PAZ00
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{ "compal,paz00", paz00_init },
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#endif
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};
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static void __init tegra_dt_init_late(void)
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{
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int i;
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tegra_init_late();
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for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
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if (of_machine_is_compatible(board_init_funcs[i].machine)) {
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board_init_funcs[i].init();
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break;
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}
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}
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}
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static const char *tegra20_dt_board_compat[] = {
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"nvidia,tegra20",
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NULL
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};
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DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
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.map_io = tegra_map_common_io,
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.init_early = tegra20_init_early,
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.init_irq = tegra_dt_init_irq,
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.handle_irq = gic_handle_irq,
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.timer = &tegra_timer,
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.init_machine = tegra_dt_init,
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.init_late = tegra_dt_init_late,
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.restart = tegra_assert_system_reset,
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.dt_compat = tegra20_dt_board_compat,
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MACHINE_END
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