61 lines
1.5 KiB
C
61 lines
1.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1997, 1999 by Ralf Baechle
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* Copyright (c) 1999 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_BCACHE_H
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#define _ASM_BCACHE_H
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/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
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chipset implemented caches. On machines with other CPUs the CPU does the
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cache thing itself. */
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struct bcache_ops {
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void (*bc_enable)(void);
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void (*bc_disable)(void);
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void (*bc_wback_inv)(unsigned long page, unsigned long size);
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void (*bc_inv)(unsigned long page, unsigned long size);
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};
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extern void indy_sc_init(void);
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extern void sni_pcimt_sc_init(void);
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#ifdef CONFIG_BOARD_SCACHE
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extern struct bcache_ops *bcops;
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static inline void bc_enable(void)
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{
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bcops->bc_enable();
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}
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static inline void bc_disable(void)
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{
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bcops->bc_disable();
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}
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static inline void bc_wback_inv(unsigned long page, unsigned long size)
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{
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bcops->bc_wback_inv(page, size);
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}
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static inline void bc_inv(unsigned long page, unsigned long size)
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{
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bcops->bc_inv(page, size);
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}
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#else /* !defined(CONFIG_BOARD_SCACHE) */
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/* Not R4000 / R4400 / R4600 / R5000. */
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#define bc_enable() do { } while (0)
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#define bc_disable() do { } while (0)
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#define bc_wback_inv(page, size) do { } while (0)
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#define bc_inv(page, size) do { } while (0)
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#endif /* !defined(CONFIG_BOARD_SCACHE) */
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#endif /* _ASM_BCACHE_H */
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