bd3d924d71
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus the IPU2 reset line and multi core CPU reset/enable bits. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
77 lines
1.8 KiB
C
77 lines
1.8 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <asm/smp_plat.h>
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#define SRC_SCR 0x000
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#define SRC_GPR1 0x020
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#define BP_SRC_SCR_WARM_RESET_ENABLE 0
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#define BP_SRC_SCR_CORE1_RST 14
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#define BP_SRC_SCR_CORE1_ENABLE 22
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static void __iomem *src_base;
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void imx_enable_cpu(int cpu, bool enable)
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{
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u32 mask, val;
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cpu = cpu_logical_map(cpu);
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mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
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val = readl_relaxed(src_base + SRC_SCR);
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val = enable ? val | mask : val & ~mask;
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writel_relaxed(val, src_base + SRC_SCR);
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}
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void imx_set_cpu_jump(int cpu, void *jump_addr)
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{
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cpu = cpu_logical_map(cpu);
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writel_relaxed(virt_to_phys(jump_addr),
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src_base + SRC_GPR1 + cpu * 8);
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}
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void imx_src_prepare_restart(void)
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{
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u32 val;
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/* clear enable bits of secondary cores */
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val = readl_relaxed(src_base + SRC_SCR);
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val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
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writel_relaxed(val, src_base + SRC_SCR);
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/* clear persistent entry register of primary core */
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writel_relaxed(0, src_base + SRC_GPR1);
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}
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void __init imx_src_init(void)
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{
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struct device_node *np;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
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if (!np)
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return;
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src_base = of_iomap(np, 0);
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WARN_ON(!src_base);
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/*
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* force warm reset sources to generate cold reset
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* for a more reliable restart
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*/
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val = readl_relaxed(src_base + SRC_SCR);
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val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
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writel_relaxed(val, src_base + SRC_SCR);
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}
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