c3b1c2de22
Several machines have the R4K cache macro name spelled incorrectly. Namely, they have cpu_has_4kcache defined instead of cpu_has_4k_cache. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle
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*
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* SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors.
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*/
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#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
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#include <cpu-feature-overrides.h>
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_4k_cache 1
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#define cpu_has_fpu 1
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#define cpu_has_32fpr 1
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#define cpu_has_counter 1
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#define cpu_has_watch 0
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#define cpu_has_mips16 0
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#define cpu_has_divec 0
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 1
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_prefetch 0
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#define cpu_has_mcheck 0
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#define cpu_has_ejtag 0
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#define cpu_has_llsc 1
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#define cpu_has_vtag_icache 0
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#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_dsp 0
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#define cpu_has_nofpuex 0
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#define cpu_has_64bits 1
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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#define cpu_has_mips32r1 0
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
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