f2b31737e5
Modules: au88x0 driver This patch extends au88x0 AC97 codec access procedures to handle multiple codecs properly. Signed-off-by: Sasha Khapyorsky <sashak@smlink.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
204 lines
6.3 KiB
C
204 lines
6.3 KiB
C
/*
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Aureal Vortex Soundcard driver.
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IO addr collected from asp4core.vxd:
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function address
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0005D5A0 13004
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00080674 14004
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00080AFF 12818
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*/
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#define CHIP_AU8820
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#define CARD_NAME "Aureal Vortex 3D Sound Processor"
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#define CARD_NAME_SHORT "au8820"
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/* Number of ADB and WT channels */
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#define NR_ADB 0x10
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#define NR_WT 0x20
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#define NR_SRC 0x10
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#define NR_A3D 0x00
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#define NR_MIXIN 0x10
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#define NR_MIXOUT 0x10
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/* ADBDMA */
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#define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */
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#define POS_MASK 0x00000fff
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#define POS_SHIFT 0x0
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#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
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#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */
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#define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */
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#define OFFSET_MASK 0x00000fff
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#define OFFSET_SHIFT 0x0
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#define IE_MASK 0x00001000 /* interrupt enable. */
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#define IE_SHIFT 0xc
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#define DIR_MASK 0x00002000 /* Direction. */
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#define DIR_SHIFT 0xd
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#define FMT_MASK 0x0003c000
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#define FMT_SHIFT 0xe
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// The masks and shift also work for the wtdma, if not specified otherwise.
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#define VORTEX_ADBDMA_BUFCFG0 0x10400
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#define VORTEX_ADBDMA_BUFCFG1 0x10404
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#define VORTEX_ADBDMA_BUFBASE 0x10200
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#define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */
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#define VORTEX_ADBDMA_STATUS 0x10600 /* stored at AdbDma->this_10 / 2 DWORD in size. */
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/* ADB */
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#define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */
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#define VORTEX_ADB_RTBASE 0x10800
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#define VORTEX_ADB_RTBASE_COUNT 103
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#define VORTEX_ADB_CHNBASE 0x1099c
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#define VORTEX_ADB_CHNBASE_COUNT 22
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#define ROUTE_MASK 0x3fff
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#define ADB_MASK 0x7f
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#define ADB_SHIFT 0x7
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//#define ADB_MIX_MASK 0xf
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/* ADB address */
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#define OFFSET_ADBDMA 0x00
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#define OFFSET_SRCOUT 0x10 /* on channel 0x11 */
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#define OFFSET_SRCIN 0x10 /* on channel < 0x11 */
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#define OFFSET_MIXOUT 0x20 /* source */
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#define OFFSET_MIXIN 0x30 /* sink */
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#define OFFSET_CODECIN 0x48 /* ADB source */
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#define OFFSET_CODECOUT 0x58 /* ADB sink/target */
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#define OFFSET_SPORTOUT 0x60 /* sink */
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#define OFFSET_SPORTIN 0x50 /* source */
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#define OFFSET_EFXOUT 0x50 /* sink */
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#define OFFSET_EFXIN 0x40 /* source */
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#define OFFSET_A3DOUT 0x00 /* This card has no HRTF :( */
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#define OFFSET_A3DIN 0x00
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#define OFFSET_WTOUT 0x58 /* */
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/* ADB route translate helper */
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#define ADB_DMA(x) (x + OFFSET_ADBDMA)
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#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
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#define ADB_SRCIN(x) (x + OFFSET_SRCIN)
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#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
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#define ADB_MIXIN(x) (x + OFFSET_MIXIN)
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#define ADB_CODECIN(x) (x + OFFSET_CODECIN)
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#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
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#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
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#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */
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#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */
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#define ADB_A3DIN(x) (x + OFFSET_A3DIN)
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#define ADB_WTOUT(x,y) (y + OFFSET_WTOUT)
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/* WTDMA */
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#define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */
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#define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */
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#define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT)
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#define WT_SUBBUF_SHIFT 0x15
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#define VORTEX_WTDMA_BUFBASE 0x10000
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#define VORTEX_WTDMA_BUFCFG0 0x10300
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#define VORTEX_WTDMA_BUFCFG1 0x10304
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#define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */
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#define VORTEX_WT_BASE 0x9000
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/* MIXER */
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#define VORTEX_MIXER_SR 0x9f00
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#define VORTEX_MIXER_CLIP 0x9f80
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#define VORTEX_MIXER_CHNBASE 0x9e40
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#define VORTEX_MIXER_RTBASE 0x9e00
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#define MIXER_RTBASE_SIZE 0x26
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#define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */
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#define VORTEX_MIX_SMP 0x9c00
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/* MIX */
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#define VORTEX_MIX_INVOL_A 0x9000 /* in? */
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#define VORTEX_MIX_INVOL_B 0x8000 /* out? */
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#define VORTEX_MIX_VOL_A 0x9800
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#define VORTEX_MIX_VOL_B 0x8800
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#define VOL_MIN 0x80 /* Input volume when muted. */
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#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
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//#define MIX_OUTL 0xe
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//#define MIX_OUTR 0xf
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//#define MIX_INL 0xe
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//#define MIX_INR 0xf
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#define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */
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#define MIX_DEFOGAIN 0x08
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/* SRC */
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#define VORTEX_SRCBLOCK_SR 0xccc0
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#define VORTEX_SRC_CHNBASE 0xcc40
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#define VORTEX_SRC_RTBASE 0xcc00
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#define VORTEX_SRC_SOURCE 0xccc4
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#define VORTEX_SRC_SOURCESIZE 0xccc8
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#define VORTEX_SRC_U0 0xce00
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#define VORTEX_SRC_DRIFT0 0xce80
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#define VORTEX_SRC_DRIFT1 0xcec0
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#define VORTEX_SRC_U1 0xcf00
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#define VORTEX_SRC_DRIFT2 0xcf40
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#define VORTEX_SRC_U2 0xcf80
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#define VORTEX_SRC_DATA 0xc800
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#define VORTEX_SRC_DATA0 0xc000
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#define VORTEX_SRC_CONVRATIO 0xce40
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//#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */
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//#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */
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/* FIFO */
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#define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */
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#define VORTEX_FIFO_WTCTRL 0xf840
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#define FIFO_RDONLY 0x00000001
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#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */
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#define FIFO_VALID 0x00000010
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#define FIFO_EMPTY 0x00000020
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#define FIFO_U0 0x00001000 /* Unknown. */
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#define FIFO_U1 0x00010000
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#define FIFO_SIZE_BITS 5
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#define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20
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#define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */
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#define VORTEX_FIFO_ADBDATA 0xe000
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#define VORTEX_FIFO_WTDATA 0xe800
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/* CODEC */
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#define VORTEX_CODEC_CTRL 0x11984
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#define VORTEX_CODEC_EN 0x11990
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#define EN_CODEC 0x00000300
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#define EN_SPORT 0x00030000
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#define EN_SPDIF 0x000c0000
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#define VORTEX_CODEC_CHN 0x11880
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#define VORTEX_CODEC_IO 0x11988
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#define VORTEX_SPDIF_FLAGS 0x1005c /* FIXME */
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#define VORTEX_SPDIF_CFG0 0x119D0
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#define VORTEX_SPDIF_CFG1 0x119D4
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#define VORTEX_SPDIF_SMPRATE 0x11994
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/* Sample timer */
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#define VORTEX_SMP_TIME 0x11998
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/* IRQ */
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#define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */
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#define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */
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#define VORTEX_STAT 0x12808 /* ?? */
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#define VORTEX_CTRL 0x1280c
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#define CTRL_MIDI_EN 0x00000001
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#define CTRL_MIDI_PORT 0x00000060
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#define CTRL_GAME_EN 0x00000008
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#define CTRL_GAME_PORT 0x00000e00
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#define CTRL_IRQ_ENABLE 0x4000
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/* write: Timer period config / read: TIMER IRQ ack. */
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#define VORTEX_IRQ_STAT 0x1199c
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/* DMA */
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#define VORTEX_DMA_BUFFER 0x10200
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#define VORTEX_ENGINE_CTRL 0x1060c
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#define ENGINE_INIT 0x0L
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/* MIDI *//* GAME. */
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#define VORTEX_MIDI_DATA 0x11000
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#define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */
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#define VORTEX_GAME_LEGACY 0x11008
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#define VORTEX_CTRL2 0x1100c
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#define CTRL2_GAME_ADCMODE 0x40
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#define VORTEX_GAME_AXIS 0x11010
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#define AXIS_SIZE 4
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#define AXIS_RANGE 0x1fff
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