d0d42df2a4
* at91: (24 commits) [ARM] 4615/4: sam926[13]ek buttons updated [ARM] 4765/1: [AT91] AT91CAP9A-DK board support [ARM] 4764/1: [AT91] AT91CAP9 core support [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation [ARM] 4761/1: [AT91] Board-support for NEW_LEDs [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200 [ARM] 4759/1: [AT91] Buttons on CSB300 [ARM] 4758/1: [AT91] LEDs [ARM] 4757/1: [AT91] UART initialization [ARM] 4756/1: [AT91] Makefile cleanup [ARM] 4755/1: [AT91] NAND update [ARM] 4754/1: [AT91] SSC library support [ARM] 4753/1: [AT91] Use DMA_BIT_MASK [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9 [ARM] 4751/1: [AT91] ISI peripheral on SAM9263 [ARM] 4750/1: [AT91] STN LCD displays on SAM9261 [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY [ARM] 4646/1: AT91: configurable HZ, default to 128 [ARM] 4688/1: at91: speed-up irq processing [ARM] 4657/1: AT91: Header definition update ... * ep93xx: [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups [ARM] 4668/1: ep93xx: implement new GPIO API * iop: [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device [ARM] 4708/1: iop: update defconfigs for 2.6.24 * kprobes: ARM kprobes: let's enable it ARM kprobes: special hook for the kprobes breakpoint handler ARM kprobes: prevent some functions involved with kprobes from being probed ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack ARM kprobes: add the kprobes hook to the page fault handler ARM kprobes: core code ARM kprobes: instruction single-stepping support * ks8695: [ARM] 4603/1: KS8695: debugfs interface to view pin state [ARM] 4601/1: KS8695: PCI support * misc: [ARM] remove duplicate includes [ARM] CONFIG_DEBUG_STACK_USAGE [ARM] 4689/1: small comment wrap fix [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS [SERIAL] 21285: Report baud rate back via termios [ARM] Remove pointless casts from void pointers, [ARM] Misc minor interrupt handler cleanups [ARM] Remove at91_lcdc.h [ARM] ARRAY_SIZE() cleanup [ARM] Update mach-types * msm: [ARM] msm: dma support for MSM7X00A [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A) [ARM] msm: irq and timer support for ARCH_MSM7X00A [ARM] msm: core platform support for ARCH_MSM7X00A * s3c2410: (33 commits) [ARM] 4795/1: S3C244X: Add armclk and setparent call [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk [ARM] 4790/1: S3C2412: Fix parent selection for msysclk. [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used. [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull() [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users [ARM] 4781/1: S3C24XX: DMA suspend and resume support [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call [ARM] 4778/1: S3C2412: Add armclk and init from DVS state [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected ... * sa1100: [ARM] sa1100: add clock source support * vfp: [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support [ARM] 4583/1: ARMv7: Add VFPv3 support [ARM] 4582/2: Add support for the common VFP subarchitecture
187 lines
4 KiB
C
187 lines
4 KiB
C
/*
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* linux/arch/arm/mach-sa1100/time.c
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*
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* Copyright (C) 1998 Deborah Wallach.
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* Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com>
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*
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* 2000/03/29 (C) Nicolas Pitre <nico@cam.org>
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* Rewritten: big cleanup, much simpler, better HZ accuracy.
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*
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/timex.h>
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#include <linux/signal.h>
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#include <linux/clocksource.h>
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#include <asm/mach/time.h>
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#include <asm/hardware.h>
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#define RTC_DEF_DIVIDER (32768 - 1)
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#define RTC_DEF_TRIM 0
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static int sa1100_set_rtc(void)
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{
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unsigned long current_time = xtime.tv_sec;
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if (RTSR & RTSR_ALE) {
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/* make sure not to forward the clock over an alarm */
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unsigned long alarm = RTAR;
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if (current_time >= alarm && alarm >= RCNR)
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return -ERESTARTSYS;
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}
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RCNR = current_time;
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return 0;
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}
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#ifdef CONFIG_NO_IDLE_HZ
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static unsigned long initial_match;
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static int match_posponed;
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#endif
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static irqreturn_t
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sa1100_timer_interrupt(int irq, void *dev_id)
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{
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unsigned int next_match;
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#ifdef CONFIG_NO_IDLE_HZ
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if (match_posponed) {
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match_posponed = 0;
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OSMR0 = initial_match;
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}
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#endif
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/*
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* Loop until we get ahead of the free running timer.
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* This ensures an exact clock tick count and time accuracy.
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* Since IRQs are disabled at this point, coherence between
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* lost_ticks(updated in do_timer()) and the match reg value is
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* ensured, hence we can use do_gettimeofday() from interrupt
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* handlers.
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*/
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do {
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timer_tick();
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OSSR = OSSR_M0; /* Clear match on timer 0 */
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next_match = (OSMR0 += LATCH);
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} while ((signed long)(next_match - OSCR) <= 0);
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return IRQ_HANDLED;
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}
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static struct irqaction sa1100_timer_irq = {
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.name = "SA11xx Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sa1100_timer_interrupt,
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};
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static cycle_t sa1100_read_oscr(void)
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{
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return OSCR;
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}
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static struct clocksource cksrc_sa1100_oscr = {
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.name = "oscr",
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.rating = 200,
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.read = sa1100_read_oscr,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init sa1100_timer_init(void)
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{
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unsigned long flags;
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set_rtc = sa1100_set_rtc;
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OIER = 0; /* disable any timer interrupts */
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OSSR = 0xf; /* clear status on all timers */
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setup_irq(IRQ_OST0, &sa1100_timer_irq);
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local_irq_save(flags);
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OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
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OSMR0 = OSCR + LATCH; /* set initial match */
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local_irq_restore(flags);
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cksrc_sa1100_oscr.mult =
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clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
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clocksource_register(&cksrc_sa1100_oscr);
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}
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#ifdef CONFIG_NO_IDLE_HZ
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static int sa1100_dyn_tick_enable_disable(void)
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{
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/* nothing to do */
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return 0;
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}
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static void sa1100_dyn_tick_reprogram(unsigned long ticks)
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{
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if (ticks > 1) {
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initial_match = OSMR0;
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OSMR0 = initial_match + ticks * LATCH;
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match_posponed = 1;
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}
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}
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static irqreturn_t
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sa1100_dyn_tick_handler(int irq, void *dev_id)
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{
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if (match_posponed) {
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match_posponed = 0;
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OSMR0 = initial_match;
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if ((signed long)(initial_match - OSCR) <= 0)
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return sa1100_timer_interrupt(irq, dev_id);
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}
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return IRQ_NONE;
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}
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static struct dyn_tick_timer sa1100_dyn_tick = {
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.enable = sa1100_dyn_tick_enable_disable,
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.disable = sa1100_dyn_tick_enable_disable,
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.reprogram = sa1100_dyn_tick_reprogram,
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.handler = sa1100_dyn_tick_handler,
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};
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#endif
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#ifdef CONFIG_PM
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unsigned long osmr[4], oier;
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static void sa1100_timer_suspend(void)
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{
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osmr[0] = OSMR0;
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osmr[1] = OSMR1;
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osmr[2] = OSMR2;
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osmr[3] = OSMR3;
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oier = OIER;
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}
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static void sa1100_timer_resume(void)
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{
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OSSR = 0x0f;
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OSMR0 = osmr[0];
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OSMR1 = osmr[1];
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OSMR2 = osmr[2];
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OSMR3 = osmr[3];
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OIER = oier;
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/*
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* OSMR0 is the system timer: make sure OSCR is sufficiently behind
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*/
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OSCR = OSMR0 - LATCH;
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}
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#else
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#define sa1100_timer_suspend NULL
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#define sa1100_timer_resume NULL
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#endif
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struct sys_timer sa1100_timer = {
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.init = sa1100_timer_init,
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.suspend = sa1100_timer_suspend,
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.resume = sa1100_timer_resume,
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#ifdef CONFIG_NO_IDLE_HZ
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.dyn_tick = &sa1100_dyn_tick,
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#endif
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};
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