b0ea0fc753
Some scalable prcmu clocks needs to be handled in conjuction with the ape opp 100 voltage. A new prcmu clock type clk_prcmu_opp_volt_scalable is implemented to handle this. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/*
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* Clocks for ux500 platforms
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*
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* Copyright (C) 2012 ST-Ericsson SA
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* Author: Ulf Hansson <ulf.hansson@linaro.org>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __UX500_CLK_H
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#define __UX500_CLK_H
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#include <linux/clk.h>
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struct clk *clk_reg_prcc_pclk(const char *name,
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const char *parent_name,
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unsigned int phy_base,
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u32 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcc_kclk(const char *name,
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const char *parent_name,
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unsigned int phy_base,
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u32 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_scalable(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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struct clk *clk_reg_prcmu_gate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_rate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_opp_gate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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#endif /* __UX500_CLK_H */
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