99532559dc
Patch from Nicolas Pitre Intel PXA27x developers manual section 5.4.1.1 lists a priority distribution for the DMA channels differently than what the code currently assumes. This patch fixes that. Noticed by Simon Vogl <vogl@soft.uni-linz.ac.at> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
64 lines
1.5 KiB
C
64 lines
1.5 KiB
C
/*
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* linux/include/asm-arm/arch-pxa/dma.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H
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/*
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* Descriptor structure for PXA's DMA engine
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* Note: this structure must always be aligned to a 16-byte boundary.
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*/
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typedef struct pxa_dma_desc {
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volatile u32 ddadr; /* Points to the next descriptor + flags */
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volatile u32 dsadr; /* DSADR value for the current transfer */
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volatile u32 dtadr; /* DTADR value for the current transfer */
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volatile u32 dcmd; /* DCMD value for the current transfer */
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} pxa_dma_desc;
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typedef enum {
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DMA_PRIO_HIGH = 0,
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DMA_PRIO_MEDIUM = 1,
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DMA_PRIO_LOW = 2
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} pxa_dma_prio;
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#if defined(CONFIG_PXA27x)
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#define PXA_DMA_CHANNELS 32
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#define pxa_for_each_dma_prio(ch, prio) \
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for ( \
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ch = prio * 4; \
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ch != (4 << prio) + 16; \
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ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
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)
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#elif defined(CONFIG_PXA25x)
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#define PXA_DMA_CHANNELS 16
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#define pxa_for_each_dma_prio(ch, prio) \
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for (ch = prio * 4; ch != (4 << prio); ch++)
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#endif
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/*
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* DMA registration
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*/
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int pxa_request_dma (char *name,
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pxa_dma_prio prio,
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void (*irq_handler)(int, void *, struct pt_regs *),
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void *data);
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void pxa_free_dma (int dma_ch);
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#endif /* _ASM_ARCH_DMA_H */
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