629e39eec8
Depending on the actual SoC we have a different base address as well as minimum and maximum size for RAM. Add these fields to the per SoC structure. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5179/
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _RALINK_COMMON_H__
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#define _RALINK_COMMON_H__
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#define RAMIPS_SYS_TYPE_LEN 32
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struct ralink_pinmux_grp {
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const char *name;
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u32 mask;
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int gpio_first;
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int gpio_last;
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};
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struct ralink_pinmux {
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struct ralink_pinmux_grp *mode;
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struct ralink_pinmux_grp *uart;
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int uart_shift;
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u32 uart_mask;
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void (*wdt_reset)(void);
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struct ralink_pinmux_grp *pci;
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int pci_shift;
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u32 pci_mask;
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};
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extern struct ralink_pinmux rt_gpio_pinmux;
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struct ralink_soc_info {
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unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
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unsigned char *compatible;
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unsigned long mem_base;
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unsigned long mem_size;
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unsigned long mem_size_min;
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unsigned long mem_size_max;
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};
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extern struct ralink_soc_info soc_info;
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extern void ralink_of_remap(void);
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extern void ralink_clk_init(void);
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extern void ralink_clk_add(const char *dev, unsigned long rate);
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extern void prom_soc_init(struct ralink_soc_info *soc_info);
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__iomem void *plat_of_remap_node(const char *node);
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#endif /* _RALINK_COMMON_H__ */
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