d1bef4ed5f
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
182 lines
4.9 KiB
C
182 lines
4.9 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Au1xxx irq map table
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/delay.h>
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#include <asm/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/mach-au1x00/au1000.h>
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#ifdef CONFIG_MIPS_PB1200
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#include <asm/mach-pb1x00/pb1200.h>
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#endif
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#ifdef CONFIG_MIPS_DB1200
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#include <asm/mach-db1x00/db1200.h>
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#define PB1200_INT_BEGIN DB1200_INT_BEGIN
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#define PB1200_INT_END DB1200_INT_END
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#endif
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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{ AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
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};
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int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
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/*
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* Support for External interrupts on the PbAu1200 Development platform.
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*/
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static volatile int pb1200_cascade_en=0;
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irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned short bisr = bcsr->int_status;
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int extirq_nr = 0;
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/* Clear all the edge interrupts. This has no effect on level */
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bcsr->int_status = bisr;
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for( ; bisr; bisr &= (bisr-1) )
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{
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extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
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/* Ack and dispatch IRQ */
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do_IRQ(extirq_nr,regs);
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}
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return IRQ_RETVAL(1);
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}
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inline void pb1200_enable_irq(unsigned int irq_nr)
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{
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bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
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bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
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}
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inline void pb1200_disable_irq(unsigned int irq_nr)
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{
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bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
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bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
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}
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static unsigned int pb1200_startup_irq( unsigned int irq_nr )
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{
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if (++pb1200_cascade_en == 1)
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{
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request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
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0, "Pb1200 Cascade", (void *)&pb1200_cascade_handler );
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#ifdef CONFIG_MIPS_PB1200
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/* We have a problem with CPLD rev3. Enable a workaround */
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if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
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{
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
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printk("updated to latest revision. This software will not\n");
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printk("work on anything less than CPLD rev4\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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printk("\nWARNING!!!\n");
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while(1);
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}
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#endif
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}
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pb1200_enable_irq(irq_nr);
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return 0;
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}
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static void pb1200_shutdown_irq( unsigned int irq_nr )
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{
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pb1200_disable_irq(irq_nr);
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if (--pb1200_cascade_en == 0)
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{
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free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
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}
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return;
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}
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static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
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{
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pb1200_disable_irq( irq_nr );
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}
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static void pb1200_end_irq(unsigned int irq_nr)
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{
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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pb1200_enable_irq(irq_nr);
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}
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}
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static struct hw_interrupt_type external_irq_type =
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{
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#ifdef CONFIG_MIPS_PB1200
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"Pb1200 Ext",
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#endif
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#ifdef CONFIG_MIPS_DB1200
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"Db1200 Ext",
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#endif
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pb1200_startup_irq,
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pb1200_shutdown_irq,
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pb1200_enable_irq,
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pb1200_disable_irq,
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pb1200_mask_and_ack_irq,
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pb1200_end_irq,
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NULL
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};
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void _board_init_irq(void)
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{
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int irq_nr;
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for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
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{
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irq_desc[irq_nr].chip = &external_irq_type;
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pb1200_disable_irq(irq_nr);
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}
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/* GPIO_7 can not be hooked here, so it is hooked upon first
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request of any source attached to the cascade */
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}
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