6209ed9d84
Commit 9d25d4db81 ("x86: BUILD_IRQ say
.text to avoid .data.percpu") added a ".text" specifier to make sure
that BUILD_IRQ() builds the irq trampoline in the text segment rather
than in some random left-over segment that the compiler happened to
leave the asm in.
However, we should also make sure that we switch back by adding a
".previous" at the end, so that there are no subtle issues with
subsequent compiler-generated code.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
222 lines
6 KiB
C
222 lines
6 KiB
C
#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sysdev.h>
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#include <linux/bitops.h>
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#include <asm/acpi.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
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#include <asm/delay.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#include <asm/i8259.h>
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/*
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* Common place to define all x86 IRQ vectors
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*
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* This builds up the IRQ handler stubs using some ugly macros in irq.h
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*
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* These macros create the low-level assembly IRQ routines that save
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* register context and call do_IRQ(). do_IRQ() then does all the
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* operations that are needed to keep the AT (or SMP IOAPIC)
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* interrupt-controller happy.
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*/
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#define IRQ_NAME2(nr) nr##_interrupt(void)
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#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
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/*
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* SMP has a few special interrupts for IPI messages
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*/
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#define BUILD_IRQ(nr) \
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asmlinkage void IRQ_NAME(nr); \
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asm("\n.text\n.p2align\n" \
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"IRQ" #nr "_interrupt:\n\t" \
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"push $~(" #nr ") ; " \
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"jmp common_interrupt\n" \
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".previous");
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#define BI(x,y) \
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BUILD_IRQ(x##y)
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#define BUILD_16_IRQS(x) \
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BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
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BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
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BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
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BI(x,c) BI(x,d) BI(x,e) BI(x,f)
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/*
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* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
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* (these are usually mapped to vectors 0x30-0x3f)
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*/
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/*
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* The IO-APIC gives us many more interrupt sources. Most of these
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* are unused but an SMP system is supposed to have enough memory ...
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* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
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* across the spectrum, so we really want to be prepared to get all
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* of these. Plus, more powerful systems might have more than 64
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* IO-APIC registers.
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*
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* (these are usually mapped into the 0x30-0xff vector range)
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*/
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BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
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BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
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BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
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BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
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#undef BUILD_16_IRQS
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#undef BI
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#define IRQ(x,y) \
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IRQ##x##y##_interrupt
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#define IRQLIST_16(x) \
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IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
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IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
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IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
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IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
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/* for the irq vectors */
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static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
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IRQLIST_16(0x2), IRQLIST_16(0x3),
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IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
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IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
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IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
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};
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#undef IRQ
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#undef IRQLIST_16
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... IRQ0_VECTOR - 1] = -1,
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[IRQ0_VECTOR] = 0,
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[IRQ1_VECTOR] = 1,
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[IRQ2_VECTOR] = 2,
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[IRQ3_VECTOR] = 3,
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[IRQ4_VECTOR] = 4,
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[IRQ5_VECTOR] = 5,
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[IRQ6_VECTOR] = 6,
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[IRQ7_VECTOR] = 7,
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[IRQ8_VECTOR] = 8,
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[IRQ9_VECTOR] = 9,
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[IRQ10_VECTOR] = 10,
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[IRQ11_VECTOR] = 11,
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[IRQ12_VECTOR] = 12,
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[IRQ13_VECTOR] = 13,
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[IRQ14_VECTOR] = 14,
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[IRQ15_VECTOR] = 15,
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[IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
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};
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static void __init init_ISA_irqs (void)
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{
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int i;
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init_bsp_APIC();
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init_8259A(0);
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for (i = 0; i < NR_IRQS; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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if (i < 16) {
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/*
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* 16 old-style INTA-cycle interrupts:
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*/
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set_irq_chip_and_handler_name(i, &i8259A_chip,
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handle_level_irq, "XT");
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} else {
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/*
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* 'high' PCI IRQs filled in on demand
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*/
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irq_desc[i].chip = &no_irq_chip;
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}
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}
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}
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void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
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void __init native_init_IRQ(void)
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{
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int i;
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init_ISA_irqs();
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/*
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* Cover the whole vector space, no vector can escape
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* us. (some of these will be overridden and become
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* 'special' SMP interrupts)
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*/
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for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
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int vector = FIRST_EXTERNAL_VECTOR + i;
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if (vector != IA32_SYSCALL_VECTOR)
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set_intr_gate(vector, interrupt[i]);
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}
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#ifdef CONFIG_SMP
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/*
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* The reschedule interrupt is a CPU-to-CPU reschedule-helper
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* IPI, driven by wakeup.
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*/
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alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
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/* IPIs for invalidation */
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
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/* IPI for generic function call */
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alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
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/* IPI for generic single function call */
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alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
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call_function_single_interrupt);
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/* Low priority IPI to cleanup after moving an irq */
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set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
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#endif
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alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
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alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
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/* self generated IPI for local APIC timer */
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alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
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/* IPI vectors for APIC spurious and error interrupts */
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alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
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alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
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if (!acpi_ioapic)
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setup_irq(2, &irq2);
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}
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