af901ca181
That is "success", "unknown", "through", "performance", "[re|un]mapping" , "access", "default", "reasonable", "[con]currently", "temperature" , "channel", "[un]used", "application", "example","hierarchy", "therefore" , "[over|under]flow", "contiguous", "threshold", "enough" and others. Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
682 lines
18 KiB
C
682 lines
18 KiB
C
/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License as published by the Free Software Foundation;
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* either version 2, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
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* the implied warranty of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE.See the GNU General Public License
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* for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "global.h"
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static void tmds_register_write(int index, u8 data);
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static int tmds_register_read(int index);
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static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
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static int check_reduce_blanking_mode(int mode_index,
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int refresh_rate);
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static int dvi_get_panel_size_from_DDCv1(void);
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static int dvi_get_panel_size_from_DDCv2(void);
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static unsigned char dvi_get_panel_info(void);
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static int viafb_dvi_query_EDID(void);
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static int check_tmds_chip(int device_id_subaddr, int device_id)
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{
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if (tmds_register_read(device_id_subaddr) == device_id)
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return OK;
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else
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return FAIL;
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}
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void viafb_init_dvi_size(void)
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{
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DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
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DEBUG_MSG(KERN_INFO
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"viaparinfo->tmds_setting_info->get_dvi_size_method %d\n",
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viaparinfo->tmds_setting_info->get_dvi_size_method);
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switch (viaparinfo->tmds_setting_info->get_dvi_size_method) {
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case GET_DVI_SIZE_BY_SYSTEM_BIOS:
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break;
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case GET_DVI_SZIE_BY_HW_STRAPPING:
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break;
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case GET_DVI_SIZE_BY_VGA_BIOS:
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default:
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dvi_get_panel_info();
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break;
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}
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return;
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}
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int viafb_tmds_trasmitter_identify(void)
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{
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unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
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/* Turn on ouputting pad */
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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/*=* DFP Low Pad on *=*/
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sr2a = viafb_read_reg(VIASR, SR2A);
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viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
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break;
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case UNICHROME_P4M900:
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case UNICHROME_P4M890:
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/* DFP Low Pad on */
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sr2a = viafb_read_reg(VIASR, SR2A);
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viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
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/* DVP0 Pad on */
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sr1e = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
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break;
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default:
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/* DVP0/DVP1 Pad on */
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sr1e = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
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BIT5 + BIT6 + BIT7);
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/* SR3E[1]Multi-function selection:
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0 = Emulate I2C and DDC bus by GPIO2/3/4. */
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sr3e = viafb_read_reg(VIASR, SR3E);
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viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
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break;
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}
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/* Check for VT1632: */
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
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viaparinfo->chip_info->tmds_chip_info.i2c_port = I2CPORTINDEX;
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if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID) != FAIL) {
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/*
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* Currently only support 12bits,dual edge,add 24bits mode later
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*/
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tmds_register_write(0x08, 0x3b);
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DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->tmds_chip_info.i2c_port);
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return OK;
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} else {
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viaparinfo->chip_info->tmds_chip_info.i2c_port = GPIOPORTINDEX;
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if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)
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!= FAIL) {
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tmds_register_write(0x08, 0x3b);
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DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_name);
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DEBUG_MSG(KERN_INFO "\n %2d",
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viaparinfo->chip_info->
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tmds_chip_info.i2c_port);
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return OK;
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}
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}
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
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if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
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((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
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(viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
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DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
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return OK;
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}
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switch (viaparinfo->chip_info->gfx_chip_name) {
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case UNICHROME_K8M890:
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viafb_write_reg(SR2A, VIASR, sr2a);
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break;
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case UNICHROME_P4M900:
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case UNICHROME_P4M890:
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viafb_write_reg(SR2A, VIASR, sr2a);
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viafb_write_reg(SR1E, VIASR, sr1e);
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break;
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default:
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viafb_write_reg(SR1E, VIASR, sr1e);
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viafb_write_reg(SR3E, VIASR, sr3e);
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break;
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}
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
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viaparinfo->chip_info->tmds_chip_info.
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tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
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return FAIL;
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}
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static void tmds_register_write(int index, u8 data)
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{
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viaparinfo->shared->i2c_stuff.i2c_port =
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viaparinfo->chip_info->tmds_chip_info.i2c_port;
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viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.
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tmds_chip_slave_addr, index,
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data);
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}
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static int tmds_register_read(int index)
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{
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u8 data;
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viaparinfo->shared->i2c_stuff.i2c_port =
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viaparinfo->chip_info->tmds_chip_info.i2c_port;
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viafb_i2c_readbyte((u8) viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_slave_addr,
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(u8) index, &data);
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return data;
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}
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static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
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{
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viaparinfo->shared->i2c_stuff.i2c_port =
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viaparinfo->chip_info->tmds_chip_info.i2c_port;
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viafb_i2c_readbytes((u8) viaparinfo->chip_info->tmds_chip_info.
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tmds_chip_slave_addr, (u8) index, buff, buff_len);
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return 0;
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}
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static int check_reduce_blanking_mode(int mode_index,
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int refresh_rate)
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{
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if (refresh_rate != 60)
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return false;
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switch (mode_index) {
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/* Following modes have reduce blanking mode. */
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case VIA_RES_1360X768:
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case VIA_RES_1400X1050:
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case VIA_RES_1440X900:
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case VIA_RES_1600X900:
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case VIA_RES_1680X1050:
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case VIA_RES_1920X1080:
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case VIA_RES_1920X1200:
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break;
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default:
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DEBUG_MSG(KERN_INFO
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"This dvi mode %d have no reduce blanking mode!\n",
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mode_index);
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return false;
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}
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return true;
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}
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/* DVI Set Mode */
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void viafb_dvi_set_mode(int video_index, int mode_bpp, int set_iga)
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{
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struct VideoModeTable *videoMode = NULL;
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struct crt_mode_table *pDviTiming;
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unsigned long desirePixelClock, maxPixelClock;
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int status = 0;
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videoMode = viafb_get_modetbl_pointer(video_index);
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pDviTiming = videoMode->crtc;
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desirePixelClock = pDviTiming->clk / 1000000;
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maxPixelClock = (unsigned long)viaparinfo->
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tmds_setting_info->max_pixel_clock;
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DEBUG_MSG(KERN_INFO "\nDVI_set_mode!!\n");
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if ((maxPixelClock != 0) && (desirePixelClock > maxPixelClock)) {
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/*Check if reduce-blanking mode is exist */
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status =
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check_reduce_blanking_mode(video_index,
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pDviTiming->refresh_rate);
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if (status) {
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video_index += 100; /*Use reduce-blanking mode */
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videoMode = viafb_get_modetbl_pointer(video_index);
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pDviTiming = videoMode->crtc;
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DEBUG_MSG(KERN_INFO
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"DVI use reduce blanking mode %d!!\n",
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video_index);
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}
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}
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viafb_fill_crtc_timing(pDviTiming, video_index, mode_bpp / 8, set_iga);
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viafb_set_output_path(DEVICE_DVI, set_iga,
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viaparinfo->chip_info->tmds_chip_info.output_interface);
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}
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/* Sense DVI Connector */
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int viafb_dvi_sense(void)
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{
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u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
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RegCR93 = 0, RegCR9B = 0, data;
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int ret = false;
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DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
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if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
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/* DI1 Pad on */
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RegSR1E = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
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/* CR6B[0]VCK Input Selection: 1 = External clock. */
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RegCR6B = viafb_read_reg(VIACR, CR6B);
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viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
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/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
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[0] Software Control Power Sequence */
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RegCR91 = viafb_read_reg(VIACR, CR91);
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viafb_write_reg(CR91, VIACR, 0x1D);
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/* CR93[7] DI1 Data Source Selection: 1 = DSP2.
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CR93[5] DI1 Clock Source: 1 = internal.
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CR93[4] DI1 Clock Polarity.
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CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
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RegCR93 = viafb_read_reg(VIACR, CR93);
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viafb_write_reg(CR93, VIACR, 0x01);
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} else {
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/* DVP0/DVP1 Pad on */
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RegSR1E = viafb_read_reg(VIASR, SR1E);
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viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
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/* SR3E[1]Multi-function selection:
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0 = Emulate I2C and DDC bus by GPIO2/3/4. */
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RegSR3E = viafb_read_reg(VIASR, SR3E);
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viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
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/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
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[0] Software Control Power Sequence */
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RegCR91 = viafb_read_reg(VIACR, CR91);
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viafb_write_reg(CR91, VIACR, 0x1D);
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/*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
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display.CR9B[2:0] DVP1 Clock Adjust */
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RegCR9B = viafb_read_reg(VIACR, CR9B);
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viafb_write_reg(CR9B, VIACR, 0x01);
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}
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data = (u8) tmds_register_read(0x09);
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if (data & 0x04)
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ret = true;
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if (ret == false) {
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if (viafb_dvi_query_EDID())
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ret = true;
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}
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/* Restore status */
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viafb_write_reg(SR1E, VIASR, RegSR1E);
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viafb_write_reg(CR91, VIACR, RegCR91);
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if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
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viafb_write_reg(CR6B, VIACR, RegCR6B);
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viafb_write_reg(CR93, VIACR, RegCR93);
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} else {
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viafb_write_reg(SR3E, VIASR, RegSR3E);
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viafb_write_reg(CR9B, VIACR, RegCR9B);
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}
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return ret;
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}
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/* Query Flat Panel's EDID Table Version Through DVI Connector */
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static int viafb_dvi_query_EDID(void)
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{
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u8 data0, data1;
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int restore;
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DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
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restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
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data0 = (u8) tmds_register_read(0x00);
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data1 = (u8) tmds_register_read(0x01);
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if ((data0 == 0) && (data1 == 0xFF)) {
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viaparinfo->chip_info->
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tmds_chip_info.tmds_chip_slave_addr = restore;
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return EDID_VERSION_1; /* Found EDID1 Table */
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}
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data0 = (u8) tmds_register_read(0x00);
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
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if (data0 == 0x20)
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return EDID_VERSION_2; /* Found EDID2 Table */
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else
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return false;
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}
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/*
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*
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* int dvi_get_panel_size_from_DDCv1(void)
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*
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* - Get Panel Size Using EDID1 Table
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*
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* Return Type: int
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*
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*/
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static int dvi_get_panel_size_from_DDCv1(void)
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{
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int i, max_h = 0, max_v = 0, tmp, restore;
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unsigned char rData;
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unsigned char EDID_DATA[18];
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DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
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restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
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viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
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rData = tmds_register_read(0x23);
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if (rData & 0x3C)
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max_h = 640;
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if (rData & 0xC0)
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max_h = 720;
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if (rData & 0x03)
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max_h = 800;
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rData = tmds_register_read(0x24);
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if (rData & 0xC0)
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max_h = 800;
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if (rData & 0x1E)
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max_h = 1024;
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if (rData & 0x01)
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max_h = 1280;
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for (i = 0x25; i < 0x6D; i++) {
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switch (i) {
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case 0x26:
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case 0x28:
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case 0x2A:
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case 0x2C:
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case 0x2E:
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case 0x30:
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case 0x32:
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case 0x34:
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rData = tmds_register_read(i);
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if (rData == 1)
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break;
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/* data = (data + 31) * 8 */
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tmp = (rData + 31) << 3;
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if (tmp > max_h)
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max_h = tmp;
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break;
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case 0x36:
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case 0x48:
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case 0x5A:
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case 0x6C:
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tmds_register_read_bytes(i, EDID_DATA, 10);
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if (!(EDID_DATA[0] || EDID_DATA[1])) {
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/* The first two byte must be zero. */
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if (EDID_DATA[3] == 0xFD) {
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/* To get max pixel clock. */
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viaparinfo->tmds_setting_info->
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max_pixel_clock = EDID_DATA[9] * 10;
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}
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}
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break;
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default:
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break;
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}
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}
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switch (max_h) {
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case 640:
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viaparinfo->tmds_setting_info->dvi_panel_size =
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VIA_RES_640X480;
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break;
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case 800:
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viaparinfo->tmds_setting_info->dvi_panel_size =
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VIA_RES_800X600;
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break;
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case 1024:
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viaparinfo->tmds_setting_info->dvi_panel_size =
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VIA_RES_1024X768;
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break;
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case 1280:
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viaparinfo->tmds_setting_info->dvi_panel_size =
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VIA_RES_1280X1024;
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break;
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case 1400:
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viaparinfo->tmds_setting_info->dvi_panel_size =
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VIA_RES_1400X1050;
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break;
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case 1440:
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viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1440X1050;
|
|
break;
|
|
case 1600:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1600X1200;
|
|
break;
|
|
case 1920:
|
|
if (max_v == 1200) {
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1920X1200;
|
|
} else {
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1920X1080;
|
|
}
|
|
|
|
break;
|
|
default:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1024X768;
|
|
DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d !\
|
|
set default panel size.\n", max_h);
|
|
break;
|
|
}
|
|
|
|
DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
|
|
viaparinfo->tmds_setting_info->max_pixel_clock);
|
|
viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
|
|
return viaparinfo->tmds_setting_info->dvi_panel_size;
|
|
}
|
|
|
|
/*
|
|
*
|
|
* int dvi_get_panel_size_from_DDCv2(void)
|
|
*
|
|
* - Get Panel Size Using EDID2 Table
|
|
*
|
|
* Return Type: int
|
|
*
|
|
*/
|
|
static int dvi_get_panel_size_from_DDCv2(void)
|
|
{
|
|
int HSize = 0, restore;
|
|
unsigned char R_Buffer[2];
|
|
|
|
DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n");
|
|
|
|
restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
|
|
viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA2;
|
|
|
|
/* Horizontal: 0x76, 0x77 */
|
|
tmds_register_read_bytes(0x76, R_Buffer, 2);
|
|
HSize = R_Buffer[0];
|
|
HSize += R_Buffer[1] << 8;
|
|
|
|
switch (HSize) {
|
|
case 640:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_640X480;
|
|
break;
|
|
case 800:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_800X600;
|
|
break;
|
|
case 1024:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1024X768;
|
|
break;
|
|
case 1280:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1280X1024;
|
|
break;
|
|
case 1400:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1400X1050;
|
|
break;
|
|
case 1440:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1440X1050;
|
|
break;
|
|
case 1600:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1600X1200;
|
|
break;
|
|
default:
|
|
viaparinfo->tmds_setting_info->dvi_panel_size =
|
|
VIA_RES_1024X768;
|
|
DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d!\
|
|
set default panel size.\n", HSize);
|
|
break;
|
|
}
|
|
|
|
viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
|
|
return viaparinfo->tmds_setting_info->dvi_panel_size;
|
|
}
|
|
|
|
/*
|
|
*
|
|
* unsigned char dvi_get_panel_info(void)
|
|
*
|
|
* - Get Panel Size
|
|
*
|
|
* Return Type: unsigned char
|
|
*/
|
|
static unsigned char dvi_get_panel_info(void)
|
|
{
|
|
unsigned char dvipanelsize;
|
|
DEBUG_MSG(KERN_INFO "dvi_get_panel_info! \n");
|
|
|
|
viafb_dvi_sense();
|
|
switch (viafb_dvi_query_EDID()) {
|
|
case 1:
|
|
dvi_get_panel_size_from_DDCv1();
|
|
break;
|
|
case 2:
|
|
dvi_get_panel_size_from_DDCv2();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
DEBUG_MSG(KERN_INFO "dvi panel size is %2d \n",
|
|
viaparinfo->tmds_setting_info->dvi_panel_size);
|
|
dvipanelsize = (unsigned char)(viaparinfo->
|
|
tmds_setting_info->dvi_panel_size);
|
|
return dvipanelsize;
|
|
}
|
|
|
|
/* If Disable DVI, turn off pad */
|
|
void viafb_dvi_disable(void)
|
|
{
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DVP0)
|
|
viafb_write_reg(SR1E, VIASR,
|
|
viafb_read_reg(VIASR, SR1E) & (~0xC0));
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DVP1)
|
|
viafb_write_reg(SR1E, VIASR,
|
|
viafb_read_reg(VIASR, SR1E) & (~0x30));
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DFP_HIGH)
|
|
viafb_write_reg(SR2A, VIASR,
|
|
viafb_read_reg(VIASR, SR2A) & (~0x0C));
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DFP_LOW)
|
|
viafb_write_reg(SR2A, VIASR,
|
|
viafb_read_reg(VIASR, SR2A) & (~0x03));
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_TMDS)
|
|
/* Turn off TMDS power. */
|
|
viafb_write_reg(CRD2, VIACR,
|
|
viafb_read_reg(VIACR, CRD2) | 0x08);
|
|
}
|
|
|
|
/* If Enable DVI, turn off pad */
|
|
void viafb_dvi_enable(void)
|
|
{
|
|
u8 data;
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DVP0) {
|
|
viafb_write_reg(SR1E, VIASR,
|
|
viafb_read_reg(VIASR, SR1E) | 0xC0);
|
|
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
|
|
tmds_register_write(0x88, 0x3b);
|
|
else
|
|
/*clear CR91[5] to direct on display period
|
|
in the secondary diplay path */
|
|
viafb_write_reg(CR91, VIACR,
|
|
viafb_read_reg(VIACR, CR91) & 0xDF);
|
|
}
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DVP1) {
|
|
viafb_write_reg(SR1E, VIASR,
|
|
viafb_read_reg(VIASR, SR1E) | 0x30);
|
|
|
|
/*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
|
|
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
|
|
tmds_register_write(0x88, 0x3b);
|
|
} else {
|
|
/*clear CR91[5] to direct on display period
|
|
in the secondary diplay path */
|
|
viafb_write_reg(CR91, VIACR,
|
|
viafb_read_reg(VIACR, CR91) & 0xDF);
|
|
}
|
|
|
|
/*fix DVI cannot enable on EPIA-M board */
|
|
if (viafb_platform_epia_dvi == 1) {
|
|
viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
|
|
viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
|
|
if (viafb_bus_width == 24) {
|
|
if (viafb_device_lcd_dualedge == 1)
|
|
data = 0x3F;
|
|
else
|
|
data = 0x37;
|
|
viafb_i2c_writebyte(viaparinfo->chip_info->
|
|
tmds_chip_info.
|
|
tmds_chip_slave_addr,
|
|
0x08, data);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DFP_HIGH) {
|
|
viafb_write_reg(SR2A, VIASR,
|
|
viafb_read_reg(VIASR, SR2A) | 0x0C);
|
|
viafb_write_reg(CR91, VIACR,
|
|
viafb_read_reg(VIACR, CR91) & 0xDF);
|
|
}
|
|
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_DFP_LOW) {
|
|
viafb_write_reg(SR2A, VIASR,
|
|
viafb_read_reg(VIASR, SR2A) | 0x03);
|
|
viafb_write_reg(CR91, VIACR,
|
|
viafb_read_reg(VIACR, CR91) & 0xDF);
|
|
}
|
|
if (viaparinfo->chip_info->
|
|
tmds_chip_info.output_interface == INTERFACE_TMDS) {
|
|
/* Turn on Display period in the panel path. */
|
|
viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
|
|
|
|
/* Turn on TMDS power. */
|
|
viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
|
|
}
|
|
}
|
|
|