Emilio López d838ff33ec clk: sunxi: add gating support to PLL1 ... This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>		2013-12-28 17:08:06 -03:00
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clk-factors.c	clk: sunxi: register factors clocks behind composite	2013-12-28 17:07:42 -03:00
clk-factors.h	clk: sunxi: register factors clocks behind composite	2013-12-28 17:07:42 -03:00
clk-sunxi.c	clk: sunxi: add gating support to PLL1	2013-12-28 17:08:06 -03:00
Makefile	clk: arm: sunxi: Add a new clock driver for sunxi SOCs	2013-03-27 08:35:34 -07:00