db0d4db22a
The GIC support code is heavily using the fact that hardware implementations are exposing banked registers. Unfortunately, it looks like at least one GIC implementation (EXYNOS) offers both the distributor and the CPU interfaces at different addresses, depending on the CPU. This problem is solved by allowing the distributor and CPU interface addresses to be per-cpu variables for the platforms that require it. The EXYNOS code is updated not to mess with the GIC internals while handling interrupts, and struct gic_chip_data is back to being private. The DT binding for the gic is updated to allow an optional "cpu-offset" value, which is used to compute the various base addresses. Finally, a new config option (GIC_NON_BANKED) is used to control this feature, so the overhead is only present on kernels compiled with support for EXYNOS. Tested on Origen (EXYNOS4) and Panda (OMAP4). Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
45 lines
523 B
Text
45 lines
523 B
Text
config ARM_GIC
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select IRQ_DOMAIN
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bool
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config GIC_NON_BANKED
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bool
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config ARM_VIC
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bool
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 3 if ARCH_S5PC100
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config ICST
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bool
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config PL330
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bool
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config SA1111
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bool
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select DMABOUNCE if !ARCH_PXA
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config DMABOUNCE
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bool
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select ZONE_DMA
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config TIMER_ACORN
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bool
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config SHARP_LOCOMO
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bool
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config SHARP_PARAM
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bool
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config SHARP_SCOOP
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bool
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