b98ac05d5e
The 44x family has an interesting "feature" which is a virtually tagged instruction cache (yuck !). So far, we haven't dealt with it properly, which means we've been mostly lucky or people didn't report the problems, unless people have been running custom patches in their distro... This is an attempt at fixing it properly. I chose to do it by setting a global flag whenever we change a PTE that was previously marked executable, and flush the entire instruction cache upon return to user space when that happens. This is a bit heavy handed, but it's hard to do more fine grained flushes as the icbi instruction, on those processor, for some very strange reasons (since the cache is virtually mapped) still requires a valid TLB entry for reading in the target address space, which isn't something I want to deal with. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
120 lines
3.1 KiB
C
120 lines
3.1 KiB
C
/*
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* Modifications by Matt Porter (mporter@mvista.com) to support
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* PPC44x Book E processors.
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*
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* This file contains the routines for initializing the MMU
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* on the 4xx series of chips.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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* Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/stddef.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <asm/pgalloc.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/uaccess.h>
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#include <asm/smp.h>
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#include <asm/bootx.h>
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#include <asm/machdep.h>
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#include <asm/setup.h>
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#include "mmu_decl.h"
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extern char etext[], _stext[];
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/* Used by the 44x TLB replacement exception handler.
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* Just needed it declared someplace.
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*/
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unsigned int tlb_44x_index = 0;
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unsigned int tlb_44x_hwater = 62;
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int icache_44x_need_flush;
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/*
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* "Pins" a 256MB TLB entry in AS0 for kernel lowmem
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*/
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static void __init
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ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
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{
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unsigned long attrib = 0;
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__asm__ __volatile__("\
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clrrwi %2,%2,10\n\
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ori %2,%2,%4\n\
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clrrwi %1,%1,10\n\
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li %0,0\n\
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ori %0,%0,%5\n\
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tlbwe %2,%3,%6\n\
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tlbwe %1,%3,%7\n\
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tlbwe %0,%3,%8"
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:
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: "r" (attrib), "r" (phys), "r" (virt), "r" (slot),
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"i" (PPC44x_TLB_VALID | PPC44x_TLB_256M),
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"i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
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"i" (PPC44x_TLB_PAGEID),
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"i" (PPC44x_TLB_XLAT),
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"i" (PPC44x_TLB_ATTRIB));
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}
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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flush_instruction_cache();
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}
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unsigned long __init mmu_mapin_ram(void)
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{
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unsigned int pinned_tlbs = 1;
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int i;
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/* Determine number of entries necessary to cover lowmem */
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pinned_tlbs = (unsigned int)
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(_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
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/* Write upper watermark to save location */
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tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
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/* If necessary, set additional pinned TLBs */
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if (pinned_tlbs > 1)
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for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
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unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE;
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ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
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}
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return total_lowmem;
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}
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