6876b3baca
This patch fixes bits of the DRM so to make the radeon DRI work on non-cache coherent PCI DMA variants of the PowerPC processors. It moves the few places that needs change to wrappers to that other architectures with similar issues can easily add their own changes to those wrappers, at least until we have more useful generic kernel API. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Airlie <airlied@linux.ie>
190 lines
5.1 KiB
C
190 lines
5.1 KiB
C
/**
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* \file ati_pcigart.c
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* ATI PCI GART support
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*
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* \author Gareth Hughes <gareth@valinux.com>
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*/
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/*
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* Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
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*
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
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static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
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struct drm_ati_pcigart_info *gart_info)
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{
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gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
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PAGE_SIZE,
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gart_info->table_mask);
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if (gart_info->table_handle == NULL)
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return -ENOMEM;
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return 0;
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}
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static void drm_ati_free_pcigart_table(struct drm_device *dev,
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struct drm_ati_pcigart_info *gart_info)
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{
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drm_pci_free(dev, gart_info->table_handle);
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gart_info->table_handle = NULL;
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}
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int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
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{
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struct drm_sg_mem *entry = dev->sg;
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unsigned long pages;
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int i;
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int max_pages;
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/* we need to support large memory configurations */
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if (!entry) {
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DRM_ERROR("no scatter/gather memory!\n");
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return 0;
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}
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if (gart_info->bus_addr) {
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max_pages = (gart_info->table_size / sizeof(u32));
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pages = (entry->pages <= max_pages)
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? entry->pages : max_pages;
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for (i = 0; i < pages; i++) {
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if (!entry->busaddr[i])
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break;
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pci_unmap_single(dev->pdev, entry->busaddr[i],
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PAGE_SIZE, PCI_DMA_TODEVICE);
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}
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
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gart_info->bus_addr = 0;
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}
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
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gart_info->table_handle) {
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drm_ati_free_pcigart_table(dev, gart_info);
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}
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return 1;
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}
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EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
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int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
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{
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struct drm_sg_mem *entry = dev->sg;
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void *address = NULL;
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unsigned long pages;
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u32 *pci_gart, page_base;
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dma_addr_t bus_address = 0;
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int i, j, ret = 0;
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int max_pages;
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if (!entry) {
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DRM_ERROR("no scatter/gather memory!\n");
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goto done;
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}
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
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DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
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ret = drm_ati_alloc_pcigart_table(dev, gart_info);
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if (ret) {
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DRM_ERROR("cannot allocate PCI GART page!\n");
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goto done;
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}
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address = gart_info->table_handle->vaddr;
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bus_address = gart_info->table_handle->busaddr;
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} else {
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address = gart_info->addr;
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bus_address = gart_info->bus_addr;
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DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
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(unsigned long long)bus_address,
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(unsigned long)address);
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}
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pci_gart = (u32 *) address;
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max_pages = (gart_info->table_size / sizeof(u32));
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pages = (entry->pages <= max_pages)
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? entry->pages : max_pages;
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memset(pci_gart, 0, max_pages * sizeof(u32));
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for (i = 0; i < pages; i++) {
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/* we need to support large memory configurations */
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entry->busaddr[i] = pci_map_single(dev->pdev,
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page_address(entry->
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pagelist[i]),
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PAGE_SIZE, PCI_DMA_TODEVICE);
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if (entry->busaddr[i] == 0) {
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DRM_ERROR("unable to map PCIGART pages!\n");
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drm_ati_pcigart_cleanup(dev, gart_info);
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address = NULL;
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bus_address = 0;
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goto done;
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}
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page_base = (u32) entry->busaddr[i];
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for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
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switch(gart_info->gart_reg_if) {
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case DRM_ATI_GART_IGP:
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*pci_gart = cpu_to_le32((page_base) | 0xc);
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break;
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case DRM_ATI_GART_PCIE:
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*pci_gart = cpu_to_le32((page_base >> 8) | 0xc);
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break;
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default:
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case DRM_ATI_GART_PCI:
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*pci_gart = cpu_to_le32(page_base);
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break;
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}
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pci_gart++;
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page_base += ATI_PCIGART_PAGE_SIZE;
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}
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}
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
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dma_sync_single_for_device(&dev->pdev->dev,
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bus_address,
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max_pages * sizeof(u32),
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PCI_DMA_TODEVICE);
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ret = 1;
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#if defined(__i386__) || defined(__x86_64__)
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wbinvd();
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#else
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mb();
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#endif
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done:
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gart_info->addr = address;
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gart_info->bus_addr = bus_address;
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return ret;
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}
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EXPORT_SYMBOL(drm_ati_pcigart_init);
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