f99e8c1d0f
Ironically, the atomic testset instruction cannot be interrupted else it will produce incorrect results. So disable interrupts to help it out. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
914 lines
15 KiB
ArmAsm
914 lines
15 KiB
ArmAsm
/*
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* Copyright 2007-2008 Analog Devices Inc.
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* Philippe Gerum <rpm@xenomai.org>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <asm/cache.h>
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#include <asm/asm-offsets.h>
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#include <asm/rwlock.h>
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#include <asm/cplb.h>
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.text
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.macro coreslot_loadaddr reg:req
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\reg\().l = _corelock;
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\reg\().h = _corelock;
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.endm
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.macro safe_testset addr:req, scratch:req
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#if ANOMALY_05000477
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cli \scratch;
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testset (\addr);
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sti \scratch;
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#else
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testset (\addr);
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#endif
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.endm
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/*
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* r0 = address of atomic data to flush and invalidate (32bit).
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*
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* Clear interrupts and return the old mask.
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* We assume that no atomic data can span cachelines.
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*
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* Clobbers: r2:0, p0
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*/
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ENTRY(_get_core_lock)
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r1 = -L1_CACHE_BYTES;
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r1 = r0 & r1;
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cli r0;
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coreslot_loadaddr p0;
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.Lretry_corelock:
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safe_testset p0, r2;
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if cc jump .Ldone_corelock;
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SSYNC(r2);
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jump .Lretry_corelock
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.Ldone_corelock:
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p0 = r1;
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CSYNC(r2);
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flushinv[p0];
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SSYNC(r2);
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rts;
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ENDPROC(_get_core_lock)
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/*
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* r0 = address of atomic data in uncacheable memory region (32bit).
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*
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* Clear interrupts and return the old mask.
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*
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* Clobbers: r0, p0
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*/
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ENTRY(_get_core_lock_noflush)
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cli r0;
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coreslot_loadaddr p0;
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.Lretry_corelock_noflush:
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safe_testset p0, r2;
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if cc jump .Ldone_corelock_noflush;
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SSYNC(r2);
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jump .Lretry_corelock_noflush
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.Ldone_corelock_noflush:
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rts;
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ENDPROC(_get_core_lock_noflush)
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/*
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* r0 = interrupt mask to restore.
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* r1 = address of atomic data to flush and invalidate (32bit).
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*
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* Interrupts are masked on entry (see _get_core_lock).
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* Clobbers: r2:0, p0
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*/
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ENTRY(_put_core_lock)
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/* Write-through cache assumed, so no flush needed here. */
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coreslot_loadaddr p0;
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r1 = 0;
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[p0] = r1;
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SSYNC(r2);
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sti r0;
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rts;
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ENDPROC(_put_core_lock)
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#ifdef __ARCH_SYNC_CORE_DCACHE
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ENTRY(___raw_smp_mark_barrier_asm)
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[--sp] = rets;
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[--sp] = ( r7:5 );
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[--sp] = r0;
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[--sp] = p1;
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[--sp] = p0;
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call _get_core_lock_noflush;
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/*
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* Calculate current core mask
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*/
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GET_CPUID(p1, r7);
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r6 = 1;
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r6 <<= r7;
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/*
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* Set bit of other cores in barrier mask. Don't change current core bit.
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*/
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p1.l = _barrier_mask;
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p1.h = _barrier_mask;
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r7 = [p1];
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r5 = r7 & r6;
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r7 = ~r6;
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cc = r5 == 0;
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if cc jump 1f;
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r7 = r7 | r6;
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1:
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[p1] = r7;
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SSYNC(r2);
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call _put_core_lock;
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p0 = [sp++];
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p1 = [sp++];
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r0 = [sp++];
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( r7:5 ) = [sp++];
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rets = [sp++];
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rts;
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ENDPROC(___raw_smp_mark_barrier_asm)
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ENTRY(___raw_smp_check_barrier_asm)
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[--sp] = rets;
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[--sp] = ( r7:5 );
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[--sp] = r0;
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[--sp] = p1;
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[--sp] = p0;
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call _get_core_lock_noflush;
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/*
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* Calculate current core mask
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*/
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GET_CPUID(p1, r7);
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r6 = 1;
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r6 <<= r7;
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/*
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* Clear current core bit in barrier mask if it is set.
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*/
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p1.l = _barrier_mask;
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p1.h = _barrier_mask;
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r7 = [p1];
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r5 = r7 & r6;
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cc = r5 == 0;
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if cc jump 1f;
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r6 = ~r6;
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r7 = r7 & r6;
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[p1] = r7;
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SSYNC(r2);
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call _put_core_lock;
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/*
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* Invalidate the entire D-cache of current core.
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*/
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sp += -12;
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call _resync_core_dcache
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sp += 12;
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jump 2f;
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1:
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call _put_core_lock;
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2:
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p0 = [sp++];
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p1 = [sp++];
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r0 = [sp++];
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( r7:5 ) = [sp++];
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rets = [sp++];
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rts;
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ENDPROC(___raw_smp_check_barrier_asm)
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/*
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* r0 = irqflags
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* r1 = address of atomic data
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*
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* Clobbers: r2:0, p1:0
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*/
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_start_lock_coherent:
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[--sp] = rets;
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[--sp] = ( r7:6 );
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r7 = r0;
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p1 = r1;
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/*
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* Determine whether the atomic data was previously
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* owned by another CPU (=r6).
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*/
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GET_CPUID(p0, r2);
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r1 = 1;
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r1 <<= r2;
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r2 = ~r1;
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r1 = [p1];
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r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
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r6 = r1 & r2;
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r1 = [p1];
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r1 <<= 4;
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r1 >>= 4;
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[p1] = r1;
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/*
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* Release the core lock now, but keep IRQs disabled while we are
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* performing the remaining housekeeping chores for the current CPU.
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*/
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coreslot_loadaddr p0;
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r1 = 0;
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[p0] = r1;
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/*
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* If another CPU has owned the same atomic section before us,
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* then our D-cached copy of the shared data protected by the
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* current spin/write_lock may be obsolete.
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*/
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cc = r6 == 0;
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if cc jump .Lcache_synced
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/*
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* Invalidate the entire D-cache of the current core.
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*/
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sp += -12;
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call _resync_core_dcache
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sp += 12;
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.Lcache_synced:
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SSYNC(r2);
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sti r7;
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( r7:6 ) = [sp++];
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rets = [sp++];
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rts
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/*
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* r0 = irqflags
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* r1 = address of atomic data
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*
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* Clobbers: r2:0, p1:0
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*/
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_end_lock_coherent:
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p1 = r1;
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GET_CPUID(p0, r2);
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r2 += 28;
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r1 = 1;
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r1 <<= r2;
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r2 = [p1];
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r2 = r1 | r2;
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[p1] = r2;
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r1 = p1;
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jump _put_core_lock;
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#endif /* __ARCH_SYNC_CORE_DCACHE */
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/*
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* r0 = &spinlock->lock
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*
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* Clobbers: r3:0, p1:0
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*/
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ENTRY(___raw_spin_is_locked_asm)
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p1 = r0;
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[--sp] = rets;
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call _get_core_lock;
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r3 = [p1];
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cc = bittst( r3, 0 );
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r3 = cc;
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r1 = p1;
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call _put_core_lock;
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rets = [sp++];
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r0 = r3;
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rts;
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ENDPROC(___raw_spin_is_locked_asm)
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/*
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* r0 = &spinlock->lock
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*
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* Clobbers: r3:0, p1:0
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*/
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ENTRY(___raw_spin_lock_asm)
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p1 = r0;
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[--sp] = rets;
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.Lretry_spinlock:
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call _get_core_lock;
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r1 = p1;
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r2 = [p1];
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cc = bittst( r2, 0 );
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if cc jump .Lbusy_spinlock
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#ifdef __ARCH_SYNC_CORE_DCACHE
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r3 = p1;
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bitset ( r2, 0 ); /* Raise the lock bit. */
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[p1] = r2;
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call _start_lock_coherent
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#else
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r2 = 1;
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[p1] = r2;
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call _put_core_lock;
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#endif
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rets = [sp++];
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rts;
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.Lbusy_spinlock:
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/* We don't touch the atomic area if busy, so that flush
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will behave like nop in _put_core_lock. */
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call _put_core_lock;
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SSYNC(r2);
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r0 = p1;
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jump .Lretry_spinlock
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ENDPROC(___raw_spin_lock_asm)
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/*
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* r0 = &spinlock->lock
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*
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* Clobbers: r3:0, p1:0
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*/
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ENTRY(___raw_spin_trylock_asm)
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p1 = r0;
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[--sp] = rets;
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call _get_core_lock;
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r1 = p1;
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r3 = [p1];
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cc = bittst( r3, 0 );
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if cc jump .Lfailed_trylock
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#ifdef __ARCH_SYNC_CORE_DCACHE
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bitset ( r3, 0 ); /* Raise the lock bit. */
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[p1] = r3;
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call _start_lock_coherent
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#else
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r2 = 1;
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[p1] = r2;
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call _put_core_lock;
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#endif
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r0 = 1;
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rets = [sp++];
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rts;
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.Lfailed_trylock:
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call _put_core_lock;
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r0 = 0;
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rets = [sp++];
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rts;
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ENDPROC(___raw_spin_trylock_asm)
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/*
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* r0 = &spinlock->lock
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*
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* Clobbers: r2:0, p1:0
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*/
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ENTRY(___raw_spin_unlock_asm)
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p1 = r0;
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[--sp] = rets;
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call _get_core_lock;
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r2 = [p1];
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bitclr ( r2, 0 );
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[p1] = r2;
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r1 = p1;
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#ifdef __ARCH_SYNC_CORE_DCACHE
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call _end_lock_coherent
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#else
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call _put_core_lock;
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#endif
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rets = [sp++];
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rts;
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ENDPROC(___raw_spin_unlock_asm)
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/*
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* r0 = &rwlock->lock
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*
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* Clobbers: r2:0, p1:0
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*/
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ENTRY(___raw_read_lock_asm)
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p1 = r0;
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[--sp] = rets;
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call _get_core_lock;
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.Lrdlock_try:
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r1 = [p1];
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r1 += -1;
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[p1] = r1;
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cc = r1 < 0;
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if cc jump .Lrdlock_failed
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r1 = p1;
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#ifdef __ARCH_SYNC_CORE_DCACHE
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call _start_lock_coherent
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#else
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call _put_core_lock;
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#endif
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rets = [sp++];
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rts;
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.Lrdlock_failed:
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r1 += 1;
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[p1] = r1;
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.Lrdlock_wait:
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r1 = p1;
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call _put_core_lock;
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SSYNC(r2);
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r0 = p1;
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call _get_core_lock;
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r1 = [p1];
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cc = r1 < 2;
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if cc jump .Lrdlock_wait;
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jump .Lrdlock_try
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ENDPROC(___raw_read_lock_asm)
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/*
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* r0 = &rwlock->lock
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*
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* Clobbers: r3:0, p1:0
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*/
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ENTRY(___raw_read_trylock_asm)
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p1 = r0;
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[--sp] = rets;
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call _get_core_lock;
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r1 = [p1];
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cc = r1 <= 0;
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if cc jump .Lfailed_tryrdlock;
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r1 += -1;
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[p1] = r1;
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r1 = p1;
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#ifdef __ARCH_SYNC_CORE_DCACHE
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call _start_lock_coherent
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#else
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call _put_core_lock;
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#endif
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rets = [sp++];
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r0 = 1;
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rts;
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.Lfailed_tryrdlock:
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r1 = p1;
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call _put_core_lock;
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rets = [sp++];
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r0 = 0;
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rts;
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ENDPROC(___raw_read_trylock_asm)
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/*
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* r0 = &rwlock->lock
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*
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* Note: Processing controlled by a reader lock should not have
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* any side-effect on cache issues with the other core, so we
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* just release the core lock and exit (no _end_lock_coherent).
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*
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* Clobbers: r3:0, p1:0
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*/
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ENTRY(___raw_read_unlock_asm)
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p1 = r0;
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[--sp] = rets;
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call _get_core_lock;
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r1 = [p1];
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r1 += 1;
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[p1] = r1;
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r1 = p1;
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call _put_core_lock;
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rets = [sp++];
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rts;
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ENDPROC(___raw_read_unlock_asm)
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/*
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* r0 = &rwlock->lock
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*
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* Clobbers: r3:0, p1:0
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*/
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ENTRY(___raw_write_lock_asm)
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p1 = r0;
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r3.l = lo(RW_LOCK_BIAS);
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r3.h = hi(RW_LOCK_BIAS);
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[--sp] = rets;
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call _get_core_lock;
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.Lwrlock_try:
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r1 = [p1];
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r1 = r1 - r3;
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#ifdef __ARCH_SYNC_CORE_DCACHE
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r2 = r1;
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r2 <<= 4;
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r2 >>= 4;
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cc = r2 == 0;
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#else
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cc = r1 == 0;
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#endif
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if !cc jump .Lwrlock_wait
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[p1] = r1;
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r1 = p1;
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#ifdef __ARCH_SYNC_CORE_DCACHE
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call _start_lock_coherent
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#else
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call _put_core_lock;
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#endif
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rets = [sp++];
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rts;
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.Lwrlock_wait:
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r1 = p1;
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call _put_core_lock;
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SSYNC(r2);
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r0 = p1;
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call _get_core_lock;
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r1 = [p1];
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#ifdef __ARCH_SYNC_CORE_DCACHE
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r1 <<= 4;
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r1 >>= 4;
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#endif
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cc = r1 == r3;
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if !cc jump .Lwrlock_wait;
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jump .Lwrlock_try
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ENDPROC(___raw_write_lock_asm)
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/*
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* r0 = &rwlock->lock
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*
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* Clobbers: r3:0, p1:0
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*/
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ENTRY(___raw_write_trylock_asm)
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p1 = r0;
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[--sp] = rets;
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call _get_core_lock;
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r1 = [p1];
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r2.l = lo(RW_LOCK_BIAS);
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r2.h = hi(RW_LOCK_BIAS);
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cc = r1 == r2;
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if !cc jump .Lfailed_trywrlock;
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#ifdef __ARCH_SYNC_CORE_DCACHE
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r1 >>= 28;
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r1 <<= 28;
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#else
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r1 = 0;
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#endif
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[p1] = r1;
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r1 = p1;
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#ifdef __ARCH_SYNC_CORE_DCACHE
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call _start_lock_coherent
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#else
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call _put_core_lock;
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#endif
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rets = [sp++];
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r0 = 1;
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rts;
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.Lfailed_trywrlock:
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r1 = p1;
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call _put_core_lock;
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rets = [sp++];
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r0 = 0;
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rts;
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ENDPROC(___raw_write_trylock_asm)
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/*
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* r0 = &rwlock->lock
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*
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* Clobbers: r3:0, p1:0
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*/
|
|
ENTRY(___raw_write_unlock_asm)
|
|
p1 = r0;
|
|
r3.l = lo(RW_LOCK_BIAS);
|
|
r3.h = hi(RW_LOCK_BIAS);
|
|
[--sp] = rets;
|
|
call _get_core_lock;
|
|
r1 = [p1];
|
|
r1 = r1 + r3;
|
|
[p1] = r1;
|
|
r1 = p1;
|
|
#ifdef __ARCH_SYNC_CORE_DCACHE
|
|
call _end_lock_coherent
|
|
#else
|
|
call _put_core_lock;
|
|
#endif
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_write_unlock_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = value
|
|
*
|
|
* Add a signed value to a 32bit word and return the new value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_atomic_update_asm)
|
|
p1 = r0;
|
|
r3 = r1;
|
|
[--sp] = rets;
|
|
call _get_core_lock;
|
|
r2 = [p1];
|
|
r3 = r3 + r2;
|
|
[p1] = r3;
|
|
r1 = p1;
|
|
call _put_core_lock;
|
|
r0 = r3;
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_atomic_update_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = mask
|
|
*
|
|
* Clear the mask bits from a 32bit word and return the old 32bit value
|
|
* atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_atomic_clear_asm)
|
|
p1 = r0;
|
|
r3 = ~r1;
|
|
[--sp] = rets;
|
|
call _get_core_lock;
|
|
r2 = [p1];
|
|
r3 = r2 & r3;
|
|
[p1] = r3;
|
|
r3 = r2;
|
|
r1 = p1;
|
|
call _put_core_lock;
|
|
r0 = r3;
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_atomic_clear_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = mask
|
|
*
|
|
* Set the mask bits into a 32bit word and return the old 32bit value
|
|
* atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_atomic_set_asm)
|
|
p1 = r0;
|
|
r3 = r1;
|
|
[--sp] = rets;
|
|
call _get_core_lock;
|
|
r2 = [p1];
|
|
r3 = r2 | r3;
|
|
[p1] = r3;
|
|
r3 = r2;
|
|
r1 = p1;
|
|
call _put_core_lock;
|
|
r0 = r3;
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_atomic_set_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = mask
|
|
*
|
|
* XOR the mask bits with a 32bit word and return the old 32bit value
|
|
* atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_atomic_xor_asm)
|
|
p1 = r0;
|
|
r3 = r1;
|
|
[--sp] = rets;
|
|
call _get_core_lock;
|
|
r2 = [p1];
|
|
r3 = r2 ^ r3;
|
|
[p1] = r3;
|
|
r3 = r2;
|
|
r1 = p1;
|
|
call _put_core_lock;
|
|
r0 = r3;
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_atomic_xor_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = mask
|
|
*
|
|
* Perform a logical AND between the mask bits and a 32bit word, and
|
|
* return the masked value. We need this on this architecture in
|
|
* order to invalidate the local cache before testing.
|
|
*
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_atomic_test_asm)
|
|
p1 = r0;
|
|
r3 = r1;
|
|
r1 = -L1_CACHE_BYTES;
|
|
r1 = r0 & r1;
|
|
p0 = r1;
|
|
flushinv[p0];
|
|
SSYNC(r2);
|
|
r0 = [p1];
|
|
r0 = r0 & r3;
|
|
rts;
|
|
ENDPROC(___raw_atomic_test_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = value
|
|
*
|
|
* Swap *ptr with value and return the old 32bit value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
#define __do_xchg(src, dst) \
|
|
p1 = r0; \
|
|
r3 = r1; \
|
|
[--sp] = rets; \
|
|
call _get_core_lock; \
|
|
r2 = src; \
|
|
dst = r3; \
|
|
r3 = r2; \
|
|
r1 = p1; \
|
|
call _put_core_lock; \
|
|
r0 = r3; \
|
|
rets = [sp++]; \
|
|
rts;
|
|
|
|
ENTRY(___raw_xchg_1_asm)
|
|
__do_xchg(b[p1] (z), b[p1])
|
|
ENDPROC(___raw_xchg_1_asm)
|
|
|
|
ENTRY(___raw_xchg_2_asm)
|
|
__do_xchg(w[p1] (z), w[p1])
|
|
ENDPROC(___raw_xchg_2_asm)
|
|
|
|
ENTRY(___raw_xchg_4_asm)
|
|
__do_xchg([p1], [p1])
|
|
ENDPROC(___raw_xchg_4_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = new
|
|
* r2 = old
|
|
*
|
|
* Swap *ptr with new if *ptr == old and return the previous *ptr
|
|
* value atomically.
|
|
*
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
#define __do_cmpxchg(src, dst) \
|
|
[--sp] = rets; \
|
|
[--sp] = r4; \
|
|
p1 = r0; \
|
|
r3 = r1; \
|
|
r4 = r2; \
|
|
call _get_core_lock; \
|
|
r2 = src; \
|
|
cc = r2 == r4; \
|
|
if !cc jump 1f; \
|
|
dst = r3; \
|
|
1: r3 = r2; \
|
|
r1 = p1; \
|
|
call _put_core_lock; \
|
|
r0 = r3; \
|
|
r4 = [sp++]; \
|
|
rets = [sp++]; \
|
|
rts;
|
|
|
|
ENTRY(___raw_cmpxchg_1_asm)
|
|
__do_cmpxchg(b[p1] (z), b[p1])
|
|
ENDPROC(___raw_cmpxchg_1_asm)
|
|
|
|
ENTRY(___raw_cmpxchg_2_asm)
|
|
__do_cmpxchg(w[p1] (z), w[p1])
|
|
ENDPROC(___raw_cmpxchg_2_asm)
|
|
|
|
ENTRY(___raw_cmpxchg_4_asm)
|
|
__do_cmpxchg([p1], [p1])
|
|
ENDPROC(___raw_cmpxchg_4_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = bitnr
|
|
*
|
|
* Set a bit in a 32bit word and return the old 32bit value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_bit_set_asm)
|
|
r2 = r1;
|
|
r1 = 1;
|
|
r1 <<= r2;
|
|
jump ___raw_atomic_set_asm
|
|
ENDPROC(___raw_bit_set_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = bitnr
|
|
*
|
|
* Clear a bit in a 32bit word and return the old 32bit value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_bit_clear_asm)
|
|
r2 = r1;
|
|
r1 = 1;
|
|
r1 <<= r2;
|
|
jump ___raw_atomic_clear_asm
|
|
ENDPROC(___raw_bit_clear_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = bitnr
|
|
*
|
|
* Toggle a bit in a 32bit word and return the old 32bit value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_bit_toggle_asm)
|
|
r2 = r1;
|
|
r1 = 1;
|
|
r1 <<= r2;
|
|
jump ___raw_atomic_xor_asm
|
|
ENDPROC(___raw_bit_toggle_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = bitnr
|
|
*
|
|
* Test-and-set a bit in a 32bit word and return the old bit value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_bit_test_set_asm)
|
|
[--sp] = rets;
|
|
[--sp] = r1;
|
|
call ___raw_bit_set_asm
|
|
r1 = [sp++];
|
|
r2 = 1;
|
|
r2 <<= r1;
|
|
r0 = r0 & r2;
|
|
cc = r0 == 0;
|
|
if cc jump 1f
|
|
r0 = 1;
|
|
1:
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_bit_test_set_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = bitnr
|
|
*
|
|
* Test-and-clear a bit in a 32bit word and return the old bit value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_bit_test_clear_asm)
|
|
[--sp] = rets;
|
|
[--sp] = r1;
|
|
call ___raw_bit_clear_asm
|
|
r1 = [sp++];
|
|
r2 = 1;
|
|
r2 <<= r1;
|
|
r0 = r0 & r2;
|
|
cc = r0 == 0;
|
|
if cc jump 1f
|
|
r0 = 1;
|
|
1:
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_bit_test_clear_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = bitnr
|
|
*
|
|
* Test-and-toggle a bit in a 32bit word,
|
|
* and return the old bit value atomically.
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_bit_test_toggle_asm)
|
|
[--sp] = rets;
|
|
[--sp] = r1;
|
|
call ___raw_bit_toggle_asm
|
|
r1 = [sp++];
|
|
r2 = 1;
|
|
r2 <<= r1;
|
|
r0 = r0 & r2;
|
|
cc = r0 == 0;
|
|
if cc jump 1f
|
|
r0 = 1;
|
|
1:
|
|
rets = [sp++];
|
|
rts;
|
|
ENDPROC(___raw_bit_test_toggle_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
* r1 = bitnr
|
|
*
|
|
* Test a bit in a 32bit word and return its value.
|
|
* We need this on this architecture in order to invalidate
|
|
* the local cache before testing.
|
|
*
|
|
* Clobbers: r3:0, p1:0
|
|
*/
|
|
ENTRY(___raw_bit_test_asm)
|
|
r2 = r1;
|
|
r1 = 1;
|
|
r1 <<= r2;
|
|
jump ___raw_atomic_test_asm
|
|
ENDPROC(___raw_bit_test_asm)
|
|
|
|
/*
|
|
* r0 = ptr
|
|
*
|
|
* Fetch and return an uncached 32bit value.
|
|
*
|
|
* Clobbers: r2:0, p1:0
|
|
*/
|
|
ENTRY(___raw_uncached_fetch_asm)
|
|
p1 = r0;
|
|
r1 = -L1_CACHE_BYTES;
|
|
r1 = r0 & r1;
|
|
p0 = r1;
|
|
flushinv[p0];
|
|
SSYNC(r2);
|
|
r0 = [p1];
|
|
rts;
|
|
ENDPROC(___raw_uncached_fetch_asm)
|