9282ed9297
Changed and simplified some page table related #defines and code. Signed-off-by: Gerald Schaefer <geraldsc@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
799 lines
24 KiB
C
799 lines
24 KiB
C
/*
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* include/asm-s390/pgtable.h
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*
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* S390 version
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* Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
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* Author(s): Hartmut Penner (hp@de.ibm.com)
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* Ulrich Weigand (weigand@de.ibm.com)
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* Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Derived from "include/asm-i386/pgtable.h"
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*/
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#ifndef _ASM_S390_PGTABLE_H
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#define _ASM_S390_PGTABLE_H
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#include <asm-generic/4level-fixup.h>
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/*
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* The Linux memory management assumes a three-level page table setup. For
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* s390 31 bit we "fold" the mid level into the top-level page table, so
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* that we physically have the same two-level page table as the s390 mmu
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* expects in 31 bit mode. For s390 64 bit we use three of the five levels
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* the hardware provides (region first and region second tables are not
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* used).
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*
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* The "pgd_xxx()" functions are trivial for a folded two-level
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* setup: the pgd is never bad, and a pmd always exists (as it's folded
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* into the pgd entry)
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*
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* This file contains the functions and defines necessary to modify and use
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* the S390 page table tree.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/bug.h>
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#include <asm/processor.h>
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#include <linux/threads.h>
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struct vm_area_struct; /* forward declaration (include/linux/mm.h) */
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struct mm_struct;
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extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
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extern void paging_init(void);
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/*
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* The S390 doesn't have any external MMU info: the kernel page
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* tables contain all the necessary information.
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*/
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#define update_mmu_cache(vma, address, pte) do { } while (0)
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern char empty_zero_page[PAGE_SIZE];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#endif /* !__ASSEMBLY__ */
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/*
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* PMD_SHIFT determines the size of the area a second-level page
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* table can map
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* PGDIR_SHIFT determines what a third-level page table entry can map
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*/
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#ifndef __s390x__
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# define PMD_SHIFT 22
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# define PGDIR_SHIFT 22
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#else /* __s390x__ */
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# define PMD_SHIFT 21
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# define PGDIR_SHIFT 31
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#endif /* __s390x__ */
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* entries per page directory level: the S390 is two-level, so
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* we don't really have any PMD directory physically.
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* for S390 segment-table entries are combined to one PGD
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* that leads to 1024 pte per pgd
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*/
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#ifndef __s390x__
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# define PTRS_PER_PTE 1024
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# define PTRS_PER_PMD 1
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# define PTRS_PER_PGD 512
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#else /* __s390x__ */
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# define PTRS_PER_PTE 512
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# define PTRS_PER_PMD 1024
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# define PTRS_PER_PGD 2048
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#endif /* __s390x__ */
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#define FIRST_USER_ADDRESS 0
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
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#ifndef __ASSEMBLY__
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/*
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* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 8MB value just means that there will be a 8MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*/
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#define VMALLOC_OFFSET (8*1024*1024)
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#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) \
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& ~(VMALLOC_OFFSET-1))
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#ifndef __s390x__
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# define VMALLOC_END (0x7fffffffL)
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#else /* __s390x__ */
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# define VMALLOC_END (0x40000000000L)
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#endif /* __s390x__ */
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/*
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* A 31 bit pagetable entry of S390 has following format:
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* | PFRA | | OS |
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* 0 0IP0
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* 00000000001111111111222222222233
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* 01234567890123456789012345678901
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*
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* I Page-Invalid Bit: Page is not available for address-translation
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* P Page-Protection Bit: Store access not possible for page
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*
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* A 31 bit segmenttable entry of S390 has following format:
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* | P-table origin | |PTL
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* 0 IC
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* 00000000001111111111222222222233
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* 01234567890123456789012345678901
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*
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* I Segment-Invalid Bit: Segment is not available for address-translation
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* C Common-Segment Bit: Segment is not private (PoP 3-30)
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* PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
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*
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* The 31 bit segmenttable origin of S390 has following format:
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*
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* |S-table origin | | STL |
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* X **GPS
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* 00000000001111111111222222222233
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* 01234567890123456789012345678901
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*
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* X Space-Switch event:
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* G Segment-Invalid Bit: *
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* P Private-Space Bit: Segment is not private (PoP 3-30)
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* S Storage-Alteration:
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* STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
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*
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* A 64 bit pagetable entry of S390 has following format:
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* | PFRA |0IP0| OS |
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* 0000000000111111111122222222223333333333444444444455555555556666
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* 0123456789012345678901234567890123456789012345678901234567890123
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*
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* I Page-Invalid Bit: Page is not available for address-translation
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* P Page-Protection Bit: Store access not possible for page
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*
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* A 64 bit segmenttable entry of S390 has following format:
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* | P-table origin | TT
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* 0000000000111111111122222222223333333333444444444455555555556666
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* 0123456789012345678901234567890123456789012345678901234567890123
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*
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* I Segment-Invalid Bit: Segment is not available for address-translation
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* C Common-Segment Bit: Segment is not private (PoP 3-30)
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* P Page-Protection Bit: Store access not possible for page
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* TT Type 00
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*
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* A 64 bit region table entry of S390 has following format:
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* | S-table origin | TF TTTL
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* 0000000000111111111122222222223333333333444444444455555555556666
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* 0123456789012345678901234567890123456789012345678901234567890123
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*
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* I Segment-Invalid Bit: Segment is not available for address-translation
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* TT Type 01
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* TF
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* TL Table lenght
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*
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* The 64 bit regiontable origin of S390 has following format:
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* | region table origon | DTTL
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* 0000000000111111111122222222223333333333444444444455555555556666
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* 0123456789012345678901234567890123456789012345678901234567890123
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*
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* X Space-Switch event:
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* G Segment-Invalid Bit:
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* P Private-Space Bit:
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* S Storage-Alteration:
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* R Real space
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* TL Table-Length:
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*
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* A storage key has the following format:
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* | ACC |F|R|C|0|
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* 0 3 4 5 6 7
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* ACC: access key
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* F : fetch protection bit
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* R : referenced bit
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* C : changed bit
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*/
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/* Hardware bits in the page table entry */
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#define _PAGE_RO 0x200 /* HW read-only */
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#define _PAGE_INVALID 0x400 /* HW invalid */
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/* Mask and six different types of pages. */
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#define _PAGE_TYPE_MASK 0x601
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#define _PAGE_TYPE_EMPTY 0x400
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#define _PAGE_TYPE_NONE 0x401
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#define _PAGE_TYPE_SWAP 0x600
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#define _PAGE_TYPE_FILE 0x601
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#define _PAGE_TYPE_RO 0x200
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#define _PAGE_TYPE_RW 0x000
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#ifndef __s390x__
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/* Bits in the segment table entry */
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#define _PAGE_TABLE_LEN 0xf /* only full page-tables */
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#define _PAGE_TABLE_COM 0x10 /* common page-table */
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#define _PAGE_TABLE_INV 0x20 /* invalid page-table */
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#define _SEG_PRESENT 0x001 /* Software (overlap with PTL) */
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/* Bits int the storage key */
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#define _PAGE_CHANGED 0x02 /* HW changed bit */
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#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
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#define _USER_SEG_TABLE_LEN 0x7f /* user-segment-table up to 2 GB */
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#define _KERNEL_SEG_TABLE_LEN 0x7f /* kernel-segment-table up to 2 GB */
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/*
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* User and Kernel pagetables are identical
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*/
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#define _PAGE_TABLE _PAGE_TABLE_LEN
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#define _KERNPG_TABLE _PAGE_TABLE_LEN
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/*
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* The Kernel segment-tables includes the User segment-table
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*/
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#define _SEGMENT_TABLE (_USER_SEG_TABLE_LEN|0x80000000|0x100)
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#define _KERNSEG_TABLE _KERNEL_SEG_TABLE_LEN
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#define USER_STD_MASK 0x00000080UL
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#else /* __s390x__ */
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/* Bits in the segment table entry */
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#define _PMD_ENTRY_INV 0x20 /* invalid segment table entry */
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#define _PMD_ENTRY 0x00
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/* Bits in the region third table entry */
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#define _PGD_ENTRY_INV 0x20 /* invalid region table entry */
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#define _PGD_ENTRY 0x07
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/*
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* User and kernel page directory
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*/
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#define _REGION_THIRD 0x4
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#define _REGION_THIRD_LEN 0x3
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#define _REGION_TABLE (_REGION_THIRD|_REGION_THIRD_LEN|0x40|0x100)
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#define _KERN_REGION_TABLE (_REGION_THIRD|_REGION_THIRD_LEN)
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#define USER_STD_MASK 0x0000000000000080UL
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/* Bits in the storage key */
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#define _PAGE_CHANGED 0x02 /* HW changed bit */
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#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
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#endif /* __s390x__ */
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/*
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* Page protection definitions.
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*/
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#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
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#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
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#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
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#define PAGE_KERNEL PAGE_RW
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#define PAGE_COPY PAGE_RO
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/*
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* The S390 can't do page protection for execute, and considers that the
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* same are read. Also, write permissions imply read permissions. This is
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* the closest we can get..
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*/
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/*xwr*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_RO
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#define __P010 PAGE_RO
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#define __P011 PAGE_RO
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#define __P100 PAGE_RO
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#define __P101 PAGE_RO
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#define __P110 PAGE_RO
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#define __P111 PAGE_RO
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#define __S000 PAGE_NONE
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#define __S001 PAGE_RO
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#define __S010 PAGE_RW
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#define __S011 PAGE_RW
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#define __S100 PAGE_RO
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#define __S101 PAGE_RO
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#define __S110 PAGE_RW
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#define __S111 PAGE_RW
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/*
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* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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static inline void set_pte(pte_t *pteptr, pte_t pteval)
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{
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*pteptr = pteval;
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}
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/*
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* pgd/pmd/pte query functions
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*/
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#ifndef __s390x__
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static inline int pgd_present(pgd_t pgd) { return 1; }
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static inline int pgd_none(pgd_t pgd) { return 0; }
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static inline int pgd_bad(pgd_t pgd) { return 0; }
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static inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _SEG_PRESENT; }
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static inline int pmd_none(pmd_t pmd) { return pmd_val(pmd) & _PAGE_TABLE_INV; }
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static inline int pmd_bad(pmd_t pmd)
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{
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return (pmd_val(pmd) & (~PAGE_MASK & ~_PAGE_TABLE_INV)) != _PAGE_TABLE;
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}
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#else /* __s390x__ */
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static inline int pgd_present(pgd_t pgd)
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{
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return (pgd_val(pgd) & ~PAGE_MASK) == _PGD_ENTRY;
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}
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static inline int pgd_none(pgd_t pgd)
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{
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return pgd_val(pgd) & _PGD_ENTRY_INV;
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}
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static inline int pgd_bad(pgd_t pgd)
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{
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return (pgd_val(pgd) & (~PAGE_MASK & ~_PGD_ENTRY_INV)) != _PGD_ENTRY;
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}
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static inline int pmd_present(pmd_t pmd)
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{
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return (pmd_val(pmd) & ~PAGE_MASK) == _PMD_ENTRY;
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}
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static inline int pmd_none(pmd_t pmd)
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{
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return pmd_val(pmd) & _PMD_ENTRY_INV;
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}
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static inline int pmd_bad(pmd_t pmd)
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{
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return (pmd_val(pmd) & (~PAGE_MASK & ~_PMD_ENTRY_INV)) != _PMD_ENTRY;
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}
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#endif /* __s390x__ */
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static inline int pte_none(pte_t pte)
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{
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return (pte_val(pte) & _PAGE_TYPE_MASK) == _PAGE_TYPE_EMPTY;
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}
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static inline int pte_present(pte_t pte)
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{
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return !(pte_val(pte) & _PAGE_INVALID) ||
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(pte_val(pte) & _PAGE_TYPE_MASK) == _PAGE_TYPE_NONE;
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}
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static inline int pte_file(pte_t pte)
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{
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return (pte_val(pte) & _PAGE_TYPE_MASK) == _PAGE_TYPE_FILE;
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}
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#define pte_same(a,b) (pte_val(a) == pte_val(b))
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/*
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* query functions pte_write/pte_dirty/pte_young only work if
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* pte_present() is true. Undefined behaviour if not..
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*/
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static inline int pte_write(pte_t pte)
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{
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return (pte_val(pte) & _PAGE_RO) == 0;
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}
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static inline int pte_dirty(pte_t pte)
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{
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/* A pte is neither clean nor dirty on s/390. The dirty bit
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* is in the storage key. See page_test_and_clear_dirty for
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* details.
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*/
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return 0;
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}
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static inline int pte_young(pte_t pte)
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{
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/* A pte is neither young nor old on s/390. The young bit
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* is in the storage key. See page_test_and_clear_young for
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* details.
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*/
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return 0;
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}
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static inline int pte_read(pte_t pte)
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{
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/* All pages are readable since we don't use the fetch
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* protection bit in the storage key.
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*/
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return 1;
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}
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/*
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* pgd/pmd/pte modification functions
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*/
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#ifndef __s390x__
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static inline void pgd_clear(pgd_t * pgdp) { }
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static inline void pmd_clear(pmd_t * pmdp)
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{
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pmd_val(pmdp[0]) = _PAGE_TABLE_INV;
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pmd_val(pmdp[1]) = _PAGE_TABLE_INV;
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pmd_val(pmdp[2]) = _PAGE_TABLE_INV;
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pmd_val(pmdp[3]) = _PAGE_TABLE_INV;
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}
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#else /* __s390x__ */
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static inline void pgd_clear(pgd_t * pgdp)
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{
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pgd_val(*pgdp) = _PGD_ENTRY_INV | _PGD_ENTRY;
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}
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static inline void pmd_clear(pmd_t * pmdp)
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{
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pmd_val(*pmdp) = _PMD_ENTRY_INV | _PMD_ENTRY;
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pmd_val1(*pmdp) = _PMD_ENTRY_INV | _PMD_ENTRY;
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}
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#endif /* __s390x__ */
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static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_val(*ptep) = _PAGE_TYPE_EMPTY;
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}
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/*
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* The following pte modification functions only work if
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* pte_present() is true. Undefined behaviour if not..
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*/
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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pte_val(pte) &= PAGE_MASK;
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pte_val(pte) |= pgprot_val(newprot);
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return pte;
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}
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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/* Do not clobber _PAGE_TYPE_NONE pages! */
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if (!(pte_val(pte) & _PAGE_INVALID))
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pte_val(pte) |= _PAGE_RO;
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return pte;
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte_val(pte) &= ~_PAGE_RO;
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return pte;
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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/* The only user of pte_mkclean is the fork() code.
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We must *not* clear the *physical* page dirty bit
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just because fork() wants to clear the dirty bit in
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*one* of the page's mappings. So we just do nothing. */
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return pte;
|
|
}
|
|
|
|
static inline pte_t pte_mkdirty(pte_t pte)
|
|
{
|
|
/* We do not explicitly set the dirty bit because the
|
|
* sske instruction is slow. It is faster to let the
|
|
* next instruction set the dirty bit.
|
|
*/
|
|
return pte;
|
|
}
|
|
|
|
static inline pte_t pte_mkold(pte_t pte)
|
|
{
|
|
/* S/390 doesn't keep its dirty/referenced bit in the pte.
|
|
* There is no point in clearing the real referenced bit.
|
|
*/
|
|
return pte;
|
|
}
|
|
|
|
static inline pte_t pte_mkyoung(pte_t pte)
|
|
{
|
|
/* S/390 doesn't keep its dirty/referenced bit in the pte.
|
|
* There is no point in setting the real referenced bit.
|
|
*/
|
|
return pte;
|
|
}
|
|
|
|
static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int
|
|
ptep_clear_flush_young(struct vm_area_struct *vma,
|
|
unsigned long address, pte_t *ptep)
|
|
{
|
|
/* No need to flush TLB; bits are in storage key */
|
|
return ptep_test_and_clear_young(vma, address, ptep);
|
|
}
|
|
|
|
static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int
|
|
ptep_clear_flush_dirty(struct vm_area_struct *vma,
|
|
unsigned long address, pte_t *ptep)
|
|
{
|
|
/* No need to flush TLB; bits are in storage key */
|
|
return ptep_test_and_clear_dirty(vma, address, ptep);
|
|
}
|
|
|
|
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
|
{
|
|
pte_t pte = *ptep;
|
|
pte_clear(mm, addr, ptep);
|
|
return pte;
|
|
}
|
|
|
|
static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
|
|
{
|
|
if (!(pte_val(*ptep) & _PAGE_INVALID)) {
|
|
#ifndef __s390x__
|
|
/* S390 has 1mb segments, we are emulating 4MB segments */
|
|
pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
|
|
#else
|
|
/* ipte in zarch mode can do the math */
|
|
pte_t *pto = ptep;
|
|
#endif
|
|
asm volatile ("ipte %2,%3"
|
|
: "=m" (*ptep) : "m" (*ptep),
|
|
"a" (pto), "a" (address) );
|
|
}
|
|
pte_val(*ptep) = _PAGE_TYPE_EMPTY;
|
|
}
|
|
|
|
static inline pte_t
|
|
ptep_clear_flush(struct vm_area_struct *vma,
|
|
unsigned long address, pte_t *ptep)
|
|
{
|
|
pte_t pte = *ptep;
|
|
|
|
__ptep_ipte(address, ptep);
|
|
return pte;
|
|
}
|
|
|
|
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
|
{
|
|
pte_t old_pte = *ptep;
|
|
set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
|
|
}
|
|
|
|
static inline void
|
|
ptep_establish(struct vm_area_struct *vma,
|
|
unsigned long address, pte_t *ptep,
|
|
pte_t entry)
|
|
{
|
|
ptep_clear_flush(vma, address, ptep);
|
|
set_pte(ptep, entry);
|
|
}
|
|
|
|
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
|
|
ptep_establish(__vma, __address, __ptep, __entry)
|
|
|
|
/*
|
|
* Test and clear dirty bit in storage key.
|
|
* We can't clear the changed bit atomically. This is a potential
|
|
* race against modification of the referenced bit. This function
|
|
* should therefore only be called if it is not mapped in any
|
|
* address space.
|
|
*/
|
|
#define page_test_and_clear_dirty(_page) \
|
|
({ \
|
|
struct page *__page = (_page); \
|
|
unsigned long __physpage = __pa((__page-mem_map) << PAGE_SHIFT); \
|
|
int __skey = page_get_storage_key(__physpage); \
|
|
if (__skey & _PAGE_CHANGED) \
|
|
page_set_storage_key(__physpage, __skey & ~_PAGE_CHANGED);\
|
|
(__skey & _PAGE_CHANGED); \
|
|
})
|
|
|
|
/*
|
|
* Test and clear referenced bit in storage key.
|
|
*/
|
|
#define page_test_and_clear_young(page) \
|
|
({ \
|
|
struct page *__page = (page); \
|
|
unsigned long __physpage = __pa((__page-mem_map) << PAGE_SHIFT); \
|
|
int __ccode; \
|
|
asm volatile ("rrbe 0,%1\n\t" \
|
|
"ipm %0\n\t" \
|
|
"srl %0,28\n\t" \
|
|
: "=d" (__ccode) : "a" (__physpage) : "cc" ); \
|
|
(__ccode & 2); \
|
|
})
|
|
|
|
/*
|
|
* Conversion functions: convert a page and protection to a page entry,
|
|
* and a page entry and page directory to the page they refer to.
|
|
*/
|
|
static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
|
|
{
|
|
pte_t __pte;
|
|
pte_val(__pte) = physpage + pgprot_val(pgprot);
|
|
return __pte;
|
|
}
|
|
|
|
#define mk_pte(pg, pgprot) \
|
|
({ \
|
|
struct page *__page = (pg); \
|
|
pgprot_t __pgprot = (pgprot); \
|
|
unsigned long __physpage = __pa((__page-mem_map) << PAGE_SHIFT); \
|
|
pte_t __pte = mk_pte_phys(__physpage, __pgprot); \
|
|
__pte; \
|
|
})
|
|
|
|
#define pfn_pte(pfn, pgprot) \
|
|
({ \
|
|
pgprot_t __pgprot = (pgprot); \
|
|
unsigned long __physpage = __pa((pfn) << PAGE_SHIFT); \
|
|
pte_t __pte = mk_pte_phys(__physpage, __pgprot); \
|
|
__pte; \
|
|
})
|
|
|
|
#ifdef __s390x__
|
|
|
|
#define pfn_pmd(pfn, pgprot) \
|
|
({ \
|
|
pgprot_t __pgprot = (pgprot); \
|
|
unsigned long __physpage = __pa((pfn) << PAGE_SHIFT); \
|
|
pmd_t __pmd = __pmd(__physpage + pgprot_val(__pgprot)); \
|
|
__pmd; \
|
|
})
|
|
|
|
#endif /* __s390x__ */
|
|
|
|
#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
|
|
#define pte_page(x) pfn_to_page(pte_pfn(x))
|
|
|
|
#define pmd_page_kernel(pmd) (pmd_val(pmd) & PAGE_MASK)
|
|
|
|
#define pmd_page(pmd) (mem_map+(pmd_val(pmd) >> PAGE_SHIFT))
|
|
|
|
#define pgd_page_kernel(pgd) (pgd_val(pgd) & PAGE_MASK)
|
|
|
|
/* to find an entry in a page-table-directory */
|
|
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
|
|
#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
|
|
|
|
/* to find an entry in a kernel page-table-directory */
|
|
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
|
|
|
#ifndef __s390x__
|
|
|
|
/* Find an entry in the second-level page table.. */
|
|
static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
|
|
{
|
|
return (pmd_t *) dir;
|
|
}
|
|
|
|
#else /* __s390x__ */
|
|
|
|
/* Find an entry in the second-level page table.. */
|
|
#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
|
|
#define pmd_offset(dir,addr) \
|
|
((pmd_t *) pgd_page_kernel(*(dir)) + pmd_index(addr))
|
|
|
|
#endif /* __s390x__ */
|
|
|
|
/* Find an entry in the third-level page table.. */
|
|
#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
|
|
#define pte_offset_kernel(pmd, address) \
|
|
((pte_t *) pmd_page_kernel(*(pmd)) + pte_index(address))
|
|
#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
|
|
#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
|
|
#define pte_unmap(pte) do { } while (0)
|
|
#define pte_unmap_nested(pte) do { } while (0)
|
|
|
|
/*
|
|
* 31 bit swap entry format:
|
|
* A page-table entry has some bits we have to treat in a special way.
|
|
* Bits 0, 20 and bit 23 have to be zero, otherwise an specification
|
|
* exception will occur instead of a page translation exception. The
|
|
* specifiation exception has the bad habit not to store necessary
|
|
* information in the lowcore.
|
|
* Bit 21 and bit 22 are the page invalid bit and the page protection
|
|
* bit. We set both to indicate a swapped page.
|
|
* Bit 30 and 31 are used to distinguish the different page types. For
|
|
* a swapped page these bits need to be zero.
|
|
* This leaves the bits 1-19 and bits 24-29 to store type and offset.
|
|
* We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
|
|
* plus 24 for the offset.
|
|
* 0| offset |0110|o|type |00|
|
|
* 0 0000000001111111111 2222 2 22222 33
|
|
* 0 1234567890123456789 0123 4 56789 01
|
|
*
|
|
* 64 bit swap entry format:
|
|
* A page-table entry has some bits we have to treat in a special way.
|
|
* Bits 52 and bit 55 have to be zero, otherwise an specification
|
|
* exception will occur instead of a page translation exception. The
|
|
* specifiation exception has the bad habit not to store necessary
|
|
* information in the lowcore.
|
|
* Bit 53 and bit 54 are the page invalid bit and the page protection
|
|
* bit. We set both to indicate a swapped page.
|
|
* Bit 62 and 63 are used to distinguish the different page types. For
|
|
* a swapped page these bits need to be zero.
|
|
* This leaves the bits 0-51 and bits 56-61 to store type and offset.
|
|
* We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
|
|
* plus 56 for the offset.
|
|
* | offset |0110|o|type |00|
|
|
* 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
|
|
* 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
|
|
*/
|
|
#ifndef __s390x__
|
|
#define __SWP_OFFSET_MASK (~0UL >> 12)
|
|
#else
|
|
#define __SWP_OFFSET_MASK (~0UL >> 11)
|
|
#endif
|
|
static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
|
|
{
|
|
pte_t pte;
|
|
offset &= __SWP_OFFSET_MASK;
|
|
pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
|
|
((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
|
|
return pte;
|
|
}
|
|
|
|
#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
|
|
#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
|
|
#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
|
|
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
|
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
|
|
|
|
#ifndef __s390x__
|
|
# define PTE_FILE_MAX_BITS 26
|
|
#else /* __s390x__ */
|
|
# define PTE_FILE_MAX_BITS 59
|
|
#endif /* __s390x__ */
|
|
|
|
#define pte_to_pgoff(__pte) \
|
|
((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
|
|
|
|
#define pgoff_to_pte(__off) \
|
|
((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
|
|
| _PAGE_TYPE_FILE })
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
#define kern_addr_valid(addr) (1)
|
|
|
|
/*
|
|
* No page table caches to initialise
|
|
*/
|
|
#define pgtable_cache_init() do { } while (0)
|
|
|
|
#define __HAVE_ARCH_PTEP_ESTABLISH
|
|
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
|
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
|
#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
|
|
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
|
|
#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
|
#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
|
|
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
|
|
#define __HAVE_ARCH_PTE_SAME
|
|
#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
|
|
#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
|
|
#include <asm-generic/pgtable.h>
|
|
|
|
#endif /* _S390_PAGE_H */
|
|
|