b7dc96d753
Most architectures have fairly simple discontiguous memory - a simple set of successive regions each containing some memory. These can be described simply as a log2 of their maximum size, along with the base address of the first region and the number of regions. The base address is already described by PHYS_PFN_OFFSET, and the number of regions via the MAX_NUMNODES and the number of online nodes. If we then supply the log2 of their maximum size, all the other discontigmem macros can move into generic code. There is one exception: lh7a40x seems to have a more complicated setup; this is left alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/*
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* linux/include/asm-arm/arch-pxa/memory.h
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*
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* Author: Nicolas Pitre
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* Copyright: (C) 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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/*
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* Physical DRAM offset.
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*/
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#define PHYS_OFFSET UL(0xa0000000)
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/*
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* Virtual view <-> DMA view memory address translations
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* virt_to_bus: Used to translate the virtual address to an
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* address suitable to be passed to set_dma_addr
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* bus_to_virt: Used to convert an address for DMA operations
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* to an address that the kernel can use.
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*/
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#define __virt_to_bus(x) __virt_to_phys(x)
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#define __bus_to_virt(x) __phys_to_virt(x)
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/*
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* The nodes are matched with the physical SDRAM banks as follows:
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*
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* node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff
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* node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
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* node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
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* node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
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*
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* This needs a node mem size of 26 bits.
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*/
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#define NODE_MEM_SIZE_BITS 26
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#endif
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